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Grant,<br>
<br>
I am developing a PCI Host driver for Keystone devices. I am trying
to understand how the device bindings work for PCI Root Complex (RC)
Host controller and corresponding devices on the bus. There are no
DT based implementation I can find for the ARM architecture. I have
seen some patches posted by Nvidia for Tegra processors. Trying to
understand how I write bindings for the host controller, the
interrupt mappings and the driver to parse these bindings.<br>
<br>
Address start /Size information from the device spec is given below.<br>
<br>
0x21800000 0x8000 /* pcie-regs
*/ <br>
0x50000000 0x10000000 /* pcie-nonprefetch
memory */ <br>
0x70000000 0x4000 /* pcie-io
*/ <br>
0x80000000 0x20000000>; /* pcie-inbound0
*/ <br>
<br>
Need
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charset=ISO-8859-1">
<font size="-1"><span style="font-family: Arial; color: black;">1:1
mapping between the Root compl<font size="-1">ex</font>
address space and the PCI memory address space</span>. In the
above it is starti<font size="-1">ng at address 0x50000000 and
size 0x10000000. <font size="-1">I see following bindings from
a power PC dts file (powerpc/boot/dts/mpc8541cds.dts)</font><br>
</font> <br>
<font size="-1"> pci1: pci@e0009000 {<br>
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;<br>
interrupt-map = <<br>
<br>
/* IDSEL 0x15 */<br>
0xa800 0x0 0x0 0x1 &mpic 0xb 0x1<br>
0xa800 0x0 0x0 0x2 &mpic 0xb 0x1<br>
0xa800 0x0 0x0 0x3 &mpic 0xb 0x1<br>
0xa800 0x0 0x0 0x4 &mpic 0xb
0x1>;<br>
interrupt-parent = <&mpic>;<br>
interrupts = <25 2>;<br>
bus-range = <0 0>;<br>
ranges = <0x2000000 0x0 0xa0000000 0xa0000000
0x0 0x20000000<br>
0x1000000 0x0 0x0 0xe3000000 0x0
0x100000>;<br>
clock-frequency = <66666666>;<br>
#interrupt-cells = <1>;<br>
#size-cells = <2>;<br>
#address-cells = <3>;<br>
reg = <0xe0009000 0x1000>;<br>
compatible = "fsl,mpc8540-pci";<br>
device_type = "pci";<br>
};<br>
</font><br>
<font size="-1">How do I <font size="-1"><font size="-1">interpret</font>
the ranges in the above bindings? I need to implement onl<font
size="-1">y Root complex functionality.<font size="-1"> <font
size="-1">Last two cell seem to repre<font size="-1">sent
size in 64 bit format (2 cells). But what does the
first 4 cells represent?<br>
<br>
<font size="-1"><font size="-1"><font size="-1">I also
need to support Legacy and MSI IRQs. There are 4
leg<font size="-1">acy IRQs going to GIC<font
size="-1">. There are 8 MSI IR<font
size="-1">Qs. How does the interrupt map
work?<br>
<br>
<font size="-1">I<font size="-1">f you
could poin<font size="-1">t me to a</font></font></font>ny
documentation that explain these, it <font
size="-1"><font size="-1"><font
size="-1">will be really helpful.
Do you t<font size="-1">hink the
above bindings represent a R<font
size="-1">oot Complex Host
controller<font size="-1"> that
I can re-use for my work?<font
size="-1"> Based on my
research so far, it app<font
size="-1">ears t<font
size="-1">hat</font> <font
size="-1">DT based dr<font
size="-1"><font
size="-1">iver
configuration<font
size="-1"> o<font
size="-1">n an</font>
ARM architec<font
size="-1">ture
would involve
devel<font
size="-1">opment
of</font><font
size="-1"><font
size="-1"> </font>OF
helper
functions
(currently <font
size="-1"><font
size="-1">implemented</font>
at different
arch level) as
well to
support the dr<font
size="-1">iver.
I believe <font
size="-1">N<font
size="-1">vdia
<font
size="-1">and
Marvell are
currently <font
size="-1">doing
this f<font
size="-1">or</font>
ARM and I <font
size="-1">may
be able to
re-use the<font
size="-1">ir
work. <br>
<br>
<font
size="-1"><font
size="-1">Thanks<br>
<br>
<font
size="-1">Murali
Karic<font
size="-1">heri<br>
<br>
</font></font><font
size="-1"></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font>
</font></font></font><br>
</font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font>
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