<div class="gmail_quote">On Thu, Dec 8, 2011 at 4:43 AM, Peter De Schrijver <span dir="ltr"><<a href="mailto:pdeschrijver@nvidia.com">pdeschrijver@nvidia.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
Rework the tegra20 clock code to support multiple tegra variants :<br>
<br>
* remove tegra2_periph_reset_assert/tegra2_periph_reset_deassert. This<br>
functionality should be in clock.c.<br>
* compile tegra_sdmmc_tap_delay only on tegra20 as this feature will not<br>
be available in future variants.<br>
* don't export clk_measure_input_freq as its functionality is also available<br>
using clk_get_rate().<br>
<br>
Signed-off-by: Peter De Schrijver <<a href="mailto:pdeschrijver@nvidia.com">pdeschrijver@nvidia.com</a>><br>
---<br>
arch/arm/mach-tegra/clock.c | 12 +++++++-----<br>
arch/arm/mach-tegra/clock.h | 8 ++++----<br>
arch/arm/mach-tegra/tegra2_clocks.c | 14 +-------------<br>
arch/arm/mach-tegra/timer.c | 12 ++++++++----<br>
4 files changed, 20 insertions(+), 26 deletions(-)<br>
<br>
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c<br>
index f8d41ff..f27bdcc 100644<br>
--- a/arch/arm/mach-tegra/clock.c<br>
+++ b/arch/arm/mach-tegra/clock.c<br>
@@ -387,13 +387,15 @@ EXPORT_SYMBOL(tegra_clk_init_from_table);<br>
<br>
void tegra_periph_reset_deassert(struct clk *c)<br>
{<br>
- tegra2_periph_reset_deassert(c);<br>
+ BUG_ON(!c->ops->reset);<br></blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">+ c->ops->reset(c, false);<br>
}<br>
EXPORT_SYMBOL(tegra_periph_reset_deassert);<br>
<br>
void tegra_periph_reset_assert(struct clk *c)<br>
{<br>
- tegra2_periph_reset_assert(c);<br>
+ BUG_ON(!c->ops->reset);<br>
+ c->ops->reset(c, true);<br>
}<br>
EXPORT_SYMBOL(tegra_periph_reset_assert);<br>
<br>
@@ -403,9 +405,9 @@ void __init tegra_init_clock(void)<br>
}<br>
<br>
/*<br>
- * The SDMMC controllers have extra bits in the clock source register that<br>
- * adjust the delay between the clock and data to compenstate for delays<br>
- * on the PCB.<br>
+ * The SDMMC controllers on tegra20 have extra bits in the clock source<br>
+ * register that adjust the delay between the clock and data to compenstate<br>
+ * for delays on the PCB.<br>
*/<br>
void tegra_sdmmc_tap_delay(struct clk *c, int delay)<br>
{<br></blockquote><div> </div><div>I created this wrapper around tegra2_sdmmc_tap_delay because I guessed the same requirement would be present in tegra3. If you don't expect this to be required on anything but tegra2, you could drop the wrapper and just have callers use tegra2_sdmmc_tap_delay.</div>
<div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h<br>
index 688316a..135bb5f 100644<br>
--- a/arch/arm/mach-tegra/clock.h<br>
+++ b/arch/arm/mach-tegra/clock.h<br>
@@ -146,15 +146,15 @@ struct tegra_clk_init_table {<br>
};<br>
<br>
void tegra2_init_clocks(void);<br>
-void tegra2_periph_reset_deassert(struct clk *c);<br>
-void tegra2_periph_reset_assert(struct clk *c);<br>
void clk_init(struct clk *clk);<br>
struct clk *tegra_get_clock_by_name(const char *name);<br>
-unsigned long clk_measure_input_freq(void);<br>
int clk_reparent(struct clk *c, struct clk *parent);<br>
void tegra_clk_init_from_table(struct tegra_clk_init_table *table);<br>
unsigned long clk_get_rate_locked(struct clk *c);<br>
int clk_set_rate_locked(struct clk *c, unsigned long rate);<br>
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC<br>
void tegra2_sdmmc_tap_delay(struct clk *c, int delay);<br>
-<br>
+#else<br>
+#define tegra2_sdmmc_tap_delay(c, d) do {} while(0);<br></blockquote><div> </div><div>It's more standard to use an empty static inline function here.</div><div><br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
+#endif<br>
#endif<br>
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c<br>
index 371869d..2ab18f6 100644<br>
--- a/arch/arm/mach-tegra/tegra2_clocks.c<br>
+++ b/arch/arm/mach-tegra/tegra2_clocks.c<br>
@@ -174,7 +174,7 @@ static int tegra_periph_clk_enable_refcount[3 * 32];<br>
#define pmc_readl(reg) \<br>
__raw_readl(reg_pmc_base + (reg))<br>
<br>
-unsigned long clk_measure_input_freq(void)<br>
+static unsigned long clk_measure_input_freq(void)<br>
{<br>
u32 clock_autodetect;<br>
clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);<br>
@@ -278,18 +278,6 @@ static struct clk_ops tegra_clk_m_ops = {<br>
.disable = tegra2_clk_m_disable,<br>
};<br>
<br>
-void tegra2_periph_reset_assert(struct clk *c)<br>
-{<br>
- BUG_ON(!c->ops->reset);<br>
- c->ops->reset(c, true);<br>
-}<br>
-<br>
-void tegra2_periph_reset_deassert(struct clk *c)<br>
-{<br>
- BUG_ON(!c->ops->reset);<br>
- c->ops->reset(c, false);<br>
-}<br>
-<br>
/* super clock functions */<br>
/* "super clocks" on tegra have two-stage muxes and a clock skipping<br>
* super divider. We will ignore the clock skipping divider, since we<br>
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c<br>
index 2f1df47..6366654 100644<br>
--- a/arch/arm/mach-tegra/timer.c<br>
+++ b/arch/arm/mach-tegra/timer.c<br>
@@ -182,14 +182,18 @@ static struct irqaction tegra_timer_irq = {<br>
static void __init tegra_init_timer(void)<br>
{<br>
struct clk *clk;<br>
- unsigned long rate = clk_measure_input_freq();<br>
+ unsigned long rate;<br>
int ret;<br>
<br>
clk = clk_get_sys("timer", NULL);<br>
- if (IS_ERR(clk))<br>
- pr_warn("Unable to get timer clock\n");<br>
- else<br>
+ if (IS_ERR(clk)) {<br>
+ pr_warn("Unable to get timer clock."<br>
+ " Assuming 12Mhz input clock.\n");<br>
+ rate = 12000000;<br>
+ } else {<br>
clk_enable(clk);<br>
+ rate = clk_get_rate(clk);<br>
+ }<br>
<br>
/*<br>
* rtc registers are used by read_persistent_clock, keep the rtc clock<br>
<span class="HOEnZb"><font color="#888888"></font></span></blockquote><div><br></div><div>This timer change should be a separate patch.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
<span class="HOEnZb"><font color="#888888">--<br>
1.7.7.rc0.72.g4b5ea.dirty<br>
<br>
</font></span></blockquote></div><br>