<br><br><div class="gmail_quote">On Wed, Jul 13, 2011 at 1:12 AM, Grant Likely <span dir="ltr"><<a href="mailto:grant.likely@secretlab.ca">grant.likely@secretlab.ca</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
On Tue, Jul 12, 2011 at 3:30 PM, Michal Simek <<a href="mailto:monstr@monstr.eu">monstr@monstr.eu</a>> wrote:<br>
> Any comments on this?<br>
<br>
Sorry I didn't comment, but this is the first I've seen it. I missed<br>
it the first time around.<br>
<br>
It's hard to provide any useful comments on this. I have no idea what<br>
FSL devices are.<br></blockquote><div><br>FSL is a point-to-point FIFO bus architecture. MicroBlaze has native ports on the CPU that allow direct connection to up to 16 master / slave pairs of these buses.<br><br>It's equivalent in some senses to the AXI streaming protocol - indeed newer MicroBlaze versions can talk AXI stream, and it will also have a role in the Zynq architecture.<br>
<br>FSL / AXI stream is a bit wierd from a device tree point of view - they are point to point, unidirectional buses - FIFOs basically. Completely different from your standard shared SoC bus. <br><br>We are looking for a good way to express this topology in the device tree. It is important to get this right - FSL and AXI stream will be an increasingly important way of connecting coprocessors and devices within Xilinx MicroBlaze and Zynq systems. We'd like to get consensus now rather than finding opposition 6-12 months from now when we try to push stuff that we've already shipped.<br>
<br>Thanks,<br><br>John<br></div></div>-- <br>John Williams, PhD, B. Eng, B. IT<br>PetaLogix - Linux Solutions for a Reconfigurable World<br>w: <a href="http://www.petalogix.com" target="_blank">www.petalogix.com</a> p: +61-7-30090663 f: +61-7-30090663<br>