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Grant, Anton,<br />
<br />
reading through the of/gpio docs and thinking about some improvements for our proprietary "ancient" code gives a lot of opportunities for major improvements ... since you are authors and your quick help in the past is really appreciated I dare to address you directly ;-)<br />
<br />
On some (mostly PowerPC) based boards we have NAND-Flash connected to a PCI FPGA.<br />
There's no NAND controller inside ... just bitbang. Currently there's an implementation using "struct nand_chip" + hooks + nand_scan() inside the pci driver. Since the driver is designed to do other things and is not available during boot (=no RFS on Nand) I definitely want to get rid of this.<br />
<br />
To me it looks like we could use the "gpio-nand" driver. All we need is registering the proper (mem mapped) GPIOs with the required names via device-tree. As far as I understand the FPGA can be considered an of_mm_gpio_chip ?<br />
<br />
Honestly I don't know how to define it using dts syntax.<br />
<br />
All we have regarding PCI is general bus ranges, devsel and irq lines ... and of course the offset inside the FPGA.<br />
I've not seen a direct representation of a PCI device - only SoC components.<br />
<br />
How am I supposed to handle the unknown (=dynamically assigned) base address ?<br />
Since the system also has PCI slots I can't make sure to always get the same adress ...<br />
<br />
<br />
Can you give some hints/advice how to define the FPGA as a GPIO-Controller ?<br />
<br />
<br />
Regards,<br />
André<br />
<br />
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