<br><tt><font size=2>Working in all feedback I received so far below now
find the new version of the </font></tt>
<br><tt><font size=2>Cell/B.E. binding DRAFT including disclaimers etc.
You'll find the core</font></tt>
<br><tt><font size=2>contents right below. Thanks.</font></tt>
<br>
<br><tt><font size=2>I removed any device_type property specifications
where not necessary according</font></tt>
<br><tt><font size=2>to IEEE Std 1275-1994 page 132 - thanks Grant and
Mitch.</font></tt>
<br>
<br><tt><font size=2>I kept the bic0 and bic1 nodes separeate, thus removing
the standard properties.</font></tt>
<br><tt><font size=2>The reason is that the location within the Cell/B.E.
processor internal MMIO address space</font></tt>
<br><tt><font size=2>is fix and needs to be defined.</font></tt>
<br>
<br><tt><font size=2>Ditto for the "mic-tm" and "pervasive"
nodes.</font></tt>
<br>
<br><tt><font size=2>I removed the "physical-id" property from
the specification.</font></tt>
<br>
<br><tt><font size=2>____________________________________________________________________________________</font></tt>
<br>
<br><tt><font size=2>DRAFT Power.org Standard for the Cell Broadband Engine
architecture device</font></tt>
<br><tt><font size=2>tree</font></tt>
<br>
<br><tt><font size=2>Draft Version 0.3 - 11 January 2009</font></tt>
<br>
<br><tt><font size=2>¸ Copyright 2008 Power.org. All rights reserved.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>Implementation of certain elements of this document
may require licenses</font></tt>
<br><tt><font size=2>under third-party intellectual
property rights, including without</font></tt>
<br><tt><font size=2>limitation, patent rights. Power.org and its
Members are not, and shall</font></tt>
<br><tt><font size=2>not be held, responsible in any manner
for identifying or failing to</font></tt>
<br><tt><font size=2>identify any or all such third-party intellectual
property rights.</font></tt>
<br>
<br><tt><font size=2>THIS POWER.ORG SPECIFICATION IS PROVIDED "AS
IS" AND WITHOUT ANY WARRANTY</font></tt>
<br><tt><font size=2>OF ANY KIND, INCLUDING, WITHOUT
LIMITATION, ANY EXPRESSED OR IMPLIED</font></tt>
<br><tt><font size=2>WARRANTY OF NON-INFRINGEMENT, MERCHANTABILITY OR FITNESS
FOR A PARTICULAR</font></tt>
<br><tt><font size=2>PURPOSE.</font></tt>
<br>
<br><tt><font size=2>IN NO EVENT SHALL POWER.ORG OR ANY MEMBER OF POWER.ORG
BE LIABLE FOR ANY</font></tt>
<br><tt><font size=2>DIRECT, INDIRECT, SPECIAL, EXEMPLARY, PUNITIVE
OR CONSEQUENTIAL DAMAGES,</font></tt>
<br><tt><font size=2>INCLUDING, WITHOUT LIMITATION, LOST
PROFITS, EVEN IF ADVISED OF THE</font></tt>
<br><tt><font size=2>POSSIBILITY OF SUCH DAMAGES.</font></tt>
<br>
<br><tt><font size=2>Questions pertaining to this document, or the terms
or conditions of its</font></tt>
<br><tt><font size=2>provision, should be addressed to:</font></tt>
<br>
<br>
<br><tt><font size=2>IEEE-ISTO</font></tt>
<br><tt><font size=2>445 Hoes Lane</font></tt>
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<br><tt><font size=2>ATTN: Power.org Board Secretary</font></tt>
<br>
<br><tt><font size=2>Introduction</font></tt>
<br>
<br><tt><font size=2>Power.org's mission is to develop, enable and promote
Power Architecture©</font></tt>
<br><tt><font size=2>technology as the preferred open standard hardware
development platform for</font></tt>
<br><tt><font size=2>the electronics industry and to administer qualification
programs that</font></tt>
<br><tt><font size=2>optimize interoperability and accelerate innovation
for a positive user</font></tt>
<br><tt><font size=2>experience. Power.org seeks to solicit the participation
of all interested</font></tt>
<br><tt><font size=2>parties on a fair, equitable and open basis.</font></tt>
<br>
<br><tt><font size=2>Power.org's output includes:</font></tt>
<br><tt><font size=2> . Open standards
and specifications</font></tt>
<br><tt><font size=2> . Business
guidelines documents</font></tt>
<br><tt><font size=2> . Best practices
and education</font></tt>
<br><tt><font size=2> . Certifications
to validate implementations and drive adoption</font></tt>
<br>
<br><tt><font size=2>Power.org's specifications enable:</font></tt>
<br><tt><font size=2> . Interoperability
between community members</font></tt>
<br><tt><font size=2> . Sustainability
built on driving open standards and convergence</font></tt>
<br>
<br><tt><font size=2>Revision History</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>|Version |Date |Editor
|Description
|</font></tt>
<br><tt><font size=2>|0.1 |20 Nov 2008|C. Rund
|Initial draft
|</font></tt>
<br><tt><font size=2>|0.2 |26 Nov 2008|C. Rund
|Ready for first internal review |</font></tt>
<br><tt><font size=2>|0.3 |11 Jan 2009|C.Rund
|Worked in the feedback from
|</font></tt>
<br><tt><font size=2>| |
| |devtree-discuss@ozlabs.org
discussion |</font></tt>
<br>
<br>
<br><tt><font size=2>Table of Contents</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>1 Overview 5</font></tt>
<br>
<br><tt><font size=2> 1.1 Scope 5</font></tt>
<br>
<br><tt><font size=2> 1.2 Purpose 5</font></tt>
<br>
<br><tt><font size=2>2 Terminology 5</font></tt>
<br>
<br><tt><font size=2> 2.1 Definitions 5</font></tt>
<br>
<br><tt><font size=2> 2.2 Abbreviations 5</font></tt>
<br>
<br><tt><font size=2> 2.3 Acronyms 5</font></tt>
<br>
<br><tt><font size=2>3 Introduction 6</font></tt>
<br>
<br><tt><font size=2>4 The Cell Broadband Engine architecture
processor representation in</font></tt>
<br><tt><font size=2>the device tree 7</font></tt>
<br>
<br><tt><font size=2> 4.1 "be" node 7</font></tt>
<br>
<br><tt><font size=2> 4.1.1 ioc node 9</font></tt>
<br>
<br><tt><font size=2> 4.1.2 "bic0" node
10</font></tt>
<br>
<br><tt><font size=2> 4.1.3 "bic1" node
11</font></tt>
<br>
<br><tt><font size=2> 4.1.4 "mic-tm"
node 11</font></tt>
<br>
<br><tt><font size=2> 4.1.5 "pervasive"
node 11</font></tt>
<br>
<br><tt><font size=2> 4.1.6 "ppe-mmio"
node 13</font></tt>
<br>
<br><tt><font size=2> 4.1.7 "interrupt-controller"
node 13</font></tt>
<br>
<br><tt><font size=2> 4.1.8 "spe" nodes
15</font></tt>
<br>
<br>
<br><tt><font size=2>DRAFT Power.org Standard for the Cell Broadband Engine
architecture device</font></tt>
<br><tt><font size=2>tree</font></tt>
<br>
<br><tt><font size=2> Overview</font></tt>
<br>
<br>
<br><tt><font size=2>1 Scope</font></tt>
<br>
<br>
<br><tt><font size=2> This document is intended
to apply the Power.org Standard for Power</font></tt>
<br><tt><font size=2> Architecture Platform Requirements
(Workstation, Server) PAPR on</font></tt>
<br><tt><font size=2> Cell Broadband Engine architecture
compliant processors. This</font></tt>
<br><tt><font size=2> encompasses requirements
therein and additional requirements for</font></tt>
<br><tt><font size=2> device tree nodes and properties
pertaining to Cell Broadband Engine</font></tt>
<br><tt><font size=2> architecture compliant
processors.</font></tt>
<br>
<br><tt><font size=2>2 Purpose</font></tt>
<br>
<br>
<br><tt><font size=2> This document is intended
to indicate the architectural option and</font></tt>
<br><tt><font size=2> feature set of Cell Broadband
Engine architecture processors to</font></tt>
<br><tt><font size=2> software via Open Firmware
(OF).</font></tt>
<br>
<br><tt><font size=2> Terminology</font></tt>
<br>
<br>
<br><tt><font size=2> This document uses definitions,
abbreviations and acronyms as</font></tt>
<br><tt><font size=2> indicated below or in
the PAPR specification [3].</font></tt>
<br>
<br><tt><font size=2>1 Definitions</font></tt>
<br>
<br>
<br><tt><font size=2> Device Tree: Open Firmware
data structure representing the set of</font></tt>
<br><tt><font size=2>
devices attached to a system. See [1] for details.</font></tt>
<br>
<br><tt><font size=2>2 Abbreviations</font></tt>
<br>
<br>
<br><tt><font size=2> Define key abbreviations
here (use "paragraph" plus tab), such as</font></tt>
<br>
<br><tt><font size=2> l.t.s.f.l.r. Leaving
this section for later revisions of this</font></tt>
<br><tt><font size=2> document - to be removed
if not used !!!!!!!!!!!!</font></tt>
<br>
<br><tt><font size=2>3 Acronyms</font></tt>
<br>
<br>
<br><tt><font size=2> Define key acronyms here
(use "paragraph" style with tabs"), such as</font></tt>
<br>
<br><tt><font size=2> EIB
Element Interconnect Bus</font></tt>
<br>
<br><tt><font size=2> IIC
Internal Interrupt Controller</font></tt>
<br>
<br><tt><font size=2> IOC
Input Output Controller</font></tt>
<br>
<br><tt><font size=2> MMIO Memory
Mapped Input Output</font></tt>
<br>
<br><tt><font size=2> OF
Open Firmware (see [1]).</font></tt>
<br>
<br><tt><font size=2> PPE
PowerPC Processing Element</font></tt>
<br>
<br><tt><font size=2> SPE
Synergistic Processing Element</font></tt>
<br>
<br>
<br>
<br><tt><font size=2> Introduction</font></tt>
<br>
<br>
<br><tt><font size=2>The specific goals of this specification are as follows:</font></tt>
<br>
<br><tt><font size=2> . To provide
the address map for the components in a Cell</font></tt>
<br><tt><font size=2> Broadband
Engine Architecture processor. Subcomponent address</font></tt>
<br><tt><font size=2> information
is detected by the OF and passed to the OS in the</font></tt>
<br><tt><font size=2> device
tree.</font></tt>
<br>
<br>
<br><tt><font size=2> . To build
upon the OF boot environment defined in IEEE 1275,</font></tt>
<br><tt><font size=2> IEEE
Standard for Boot (Initialization Configuration) Firmware:</font></tt>
<br><tt><font size=2> Core
Requirements and Practices.</font></tt>
<br>
<br>
<br><tt><font size=2> . To provide
device tree nodes and property values necessary for</font></tt>
<br><tt><font size=2> access
to and configuration of the Cell Broadband Engine</font></tt>
<br><tt><font size=2> Architecture
processor subcomponents.</font></tt>
<br>
<br><tt><font size=2>The Cell Broadband Engine architecture processors
are implemented as</font></tt>
<br><tt><font size=2>systems on a chip. Besides a PowerPC processor it
contains eight</font></tt>
<br><tt><font size=2>Synergistic Processing Elements (SPEs) in addition.
Each SPE has access to</font></tt>
<br><tt><font size=2>256kB of associated local store. All logic of the
non-processor part is</font></tt>
<br><tt><font size=2>accessed via MMIO. Mapping and structure of the MMIO
space are described</font></tt>
<br><tt><font size=2>with the "be" node. A nodes' unit
address is the MMIO address of that</font></tt>
<br><tt><font size=2>particular BE. The "be" node is located
in the device tree as child of the</font></tt>
<br><tt><font size=2>root node '/'.</font></tt>
<br>
<br><tt><font size=2> The Cell Broadband Engine architecture
processor representation in the</font></tt>
<br><tt><font size=2> device tree</font></tt>
<br>
<br>
<br><tt><font size=2>The following contents are outlined according to the
hierarchy of the</font></tt>
<br><tt><font size=2>components in the sub-tree containing the components
of the Cell Broadband</font></tt>
<br><tt><font size=2>Engine processor.</font></tt>
<br>
<br><tt><font size=2>All device tree nodes detailed below contain a "name"
property in addition</font></tt>
<br><tt><font size=2>to the mentioned properties as follows</font></tt>
<br>
<br><tt><font size=2> . Specifies
the name of the node</font></tt>
<br>
<br>
<br><tt><font size=2> . Encoded
as with encode-string</font></tt>
<br>
<br>
<br><tt><font size=2> . Default
is the name of the node</font></tt>
<br>
<br>
<br><tt><font size=2> Throughout
the description below the notation</font></tt>
<br><tt><font size=2> phandle(<expression>)
is used to retrieve the phandle of a</font></tt>
<br><tt><font size=2> node.
A phandle of a device tree node is the cell-sized datum</font></tt>
<br><tt><font size=2> identifying
the particular device tree node.</font></tt>
<br>
<br><tt><font size=2>1 "be" node</font></tt>
<br>
<br>
<br><tt><font size=2>The "be" node contains a set of properties
and sub-nodes, which describe</font></tt>
<br><tt><font size=2>the structure of a Cell Broadband Engine Architecture
processor. All the</font></tt>
<br><tt><font size=2>devices are contained, except the Power PC processor
core nodes, which are</font></tt>
<br><tt><font size=2>located under the "/cpus" path according
to the PowerPC Processor binding</font></tt>
<br><tt><font size=2>to the IEEE 1275 standard.</font></tt>
<br>
<br><tt><font size=2>"reg" property</font></tt>
<br>
<br><tt><font size=2> Standard
property name specifying the < address, size > pair of</font></tt>
<br><tt><font size=2> the
Cell Broadband Engine processor's MMIO mapped registers.</font></tt>
<br>
<br>
<br><tt><font size=2> Prop-encoded
array: Encoded as with encode-phys for the</font></tt>
<br><tt><font size=2> address.
The size part is encoded with two encode-ints.</font></tt>
<br>
<br>
<br><tt><font size=2> The
array consists of four 32-bit values. Value one and two in</font></tt>
<br><tt><font size=2> this
array correspond to the 64-bit address value the the Cell</font></tt>
<br><tt><font size=2> Broadband
Engine Architecture processor is mapped into. Value</font></tt>
<br><tt><font size=2> three
and four correspond to the 64-bit size. Both pairs</font></tt>
<br><tt><font size=2> represent
the < address, size > pair of MMIO mapped registers</font></tt>
<br><tt><font size=2> in
the Cell Broadband Engine processor's MMIO mapped register</font></tt>
<br><tt><font size=2> space.</font></tt>
<br>
<br>
<br><tt><font size=2> Default
value is { 0x00000iii 0x00000000 0x00000000 0x000800000</font></tt>
<br><tt><font size=2> },
where iii is the offset defined by the hardware settings.</font></tt>
<br>
<br><tt><font size=2>"ranges" property</font></tt>
<br>
<br><tt><font size=2> Standard
property name which specifies the mapping of the child</font></tt>
<br><tt><font size=2> of
the "be" node within the "be" nodes' parent address
space</font></tt>
<br><tt><font size=2> using
the < child, parent, size > triple.</font></tt>
<br>
<br>
<br><tt><font size=2> Prop-encoded
array: Encoded as with encode-int for the childs</font></tt>
<br><tt><font size=2> range,
encode-phys for the parents range and encode-int for the</font></tt>
<br><tt><font size=2> size.</font></tt>
<br>
<br>
<br><tt><font size=2> The
array consists of four 32-bit values. Value one in this</font></tt>
<br><tt><font size=2> array
corresponds to the 32-bit child address encoded as with</font></tt>
<br><tt><font size=2> encode-int.
Value two and three correspond to the 64-bit parent</font></tt>
<br><tt><font size=2> address
encoded as with encode-phys. Value three in this array</font></tt>
<br><tt><font size=2> corresponds
to the 32-bit size.</font></tt>
<br>
<br>
<br><tt><font size=2> Default
value is { 0x00000000 0x00000iii 0x00000000 0x00080000</font></tt>
<br><tt><font size=2> },
mapping address 0 of child to 0x00000iii 00000000.</font></tt>
<br>
<br><tt><font size=2>"model" property</font></tt>
<br>
<br>
<br><tt><font size=2> property
name: Specifies model of node.</font></tt>
<br>
<br>
<br><tt><font size=2> Encoded
as with encode-string.</font></tt>
<br>
<br>
<br><tt><font size=2> Default
value is { "IBM,CBEA" }.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"ibm,dt-version" property</font></tt>
<br>
<br><tt><font size=2>property name: Specifies the current device tree version
number. The</font></tt>
<br><tt><font size=2>version number format is major.minor.</font></tt>
<br>
<br><tt><font size=2>Whenever the device tree is changed or extended in
a way that OS changes</font></tt>
<br><tt><font size=2>are required the major version is changed.</font></tt>
<br>
<br><tt><font size=2>The minor version is changed when at least one new
property is added or</font></tt>
<br><tt><font size=2>removed.</font></tt>
<br>
<br><tt><font size=2>Encoded as with encode-string</font></tt>
<br>
<br><tt><font size=2>The default value is { 1.1 }</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"#address-cells" property</font></tt>
<br>
<br>
<br><tt><font size=2>property name which specifies the number of address
cells for child nodes</font></tt>
<br><tt><font size=2> to the current node.</font></tt>
<br>
<br>
<br><tt><font size=2> Encoded
as with encode-int.</font></tt>
<br>
<br>
<br><tt><font size=2> Default
value is { 1 }</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"#size-cells" property</font></tt>
<br>
<br><tt><font size=2>Standard property name which specifies the number
of size cells for child</font></tt>
<br><tt><font size=2>nodes to the current node.</font></tt>
<br>
<br><tt><font size=2>Encoded as with encode-int.</font></tt>
<br>
<br><tt><font size=2>Default value is { 1 }</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"ibm,associativity" property</font></tt>
<br>
<br><tt><font size=2>property name: Property to define the associativity
domains for this</font></tt>
<br><tt><font size=2>resource.</font></tt>
<br><tt><font size=2>See Power Architecture Platform Requirements (PAPR)
[3], Sections</font></tt>
<br><tt><font size=2>14.11.2.2, 15.2, 15.3, 18.3 and C.6.2.2 for details
on this property.</font></tt>
<br>
<br><tt><font size=2>Set values to { 4 0x00000000, 0x00000000, 0x0000000i,
0x0000000i }; i = 0</font></tt>
<br><tt><font size=2>for associativity to Cell Broadband Engine processor
0, i = 1 for</font></tt>
<br><tt><font size=2>associativity to Cell Broadband Engine processor 1.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"interrupt-parent" property</font></tt>
<br>
<br><tt><font size=2>property name: Property that specifies the interrupt
handler responsible</font></tt>
<br><tt><font size=2>for this node.</font></tt>
<br>
<br><tt><font size=2>The value represents a phandle of the interrupt handler
node, encoded as</font></tt>
<br><tt><font size=2>with encode-int.</font></tt>
<br>
<br><tt><font size=2>Default value is { phandle( my-self/interrupt-controller)
}</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"cpus" property</font></tt>
<br>
<br><tt><font size=2>property name: Porperty to specify the PPE component
of the Cell Broadband</font></tt>
<br><tt><font size=2>Engine architecture processor chip.</font></tt>
<br>
<br><tt><font size=2>phandle of the cpu node, encoded as with encode-int.</font></tt>
<br>
<br><tt><font size=2>Default value is { phandle(/cpus/PowerPC,BE@i) };
i = 0 for Cell Broadband</font></tt>
<br><tt><font size=2>Engine Architecture processor 0, i = 1 for Cell Broadband
Engine</font></tt>
<br><tt><font size=2>Architecture processor 1.</font></tt>
<br>
<br><tt><font size=2>1 ioc node</font></tt>
<br>
<br>
<br><tt><font size=2>The Input/Output Controller (IOC) node contains among
others the properties</font></tt>
<br><tt><font size=2>specifying the address range of MMIO register space
controlling the IOC.</font></tt>
<br>
<br><tt><font size=2>"reg" property</font></tt>
<br>
<br><tt><font size=2>Default property name: Property to specify the MMIO
offset of the IOC,</font></tt>
<br><tt><font size=2>which are two sets of registers each represented by
an < offset, size ></font></tt>
<br><tt><font size=2>pair.</font></tt>
<br>
<br><tt><font size=2>prop-encoded-array: Encoded as with encode-phys for
the offset values,</font></tt>
<br><tt><font size=2>encode-int for the size values.</font></tt>
<br>
<br><tt><font size=2>The array consists of four 32-bit values to represent
two < offset, size ></font></tt>
<br><tt><font size=2>pairs. Value one in this array corresponds to the
first offset value within</font></tt>
<br><tt><font size=2>the child address space, encoded as with encode-phys.
Value two corresponds</font></tt>
<br><tt><font size=2>to the size, encoded as with encode-int. Value three
in this array</font></tt>
<br><tt><font size=2>corresponds to the second offset value, value four
to the second size.</font></tt>
<br><tt><font size=2>The spaces belong to two different units:</font></tt>
<br>
<br><tt><font size=2> 1. 0x00510xxx covers the IOC Address
Translation MMIO Registers, whereras</font></tt>
<br><tt><font size=2> 2. 0x00511xxx covers the I/O Command
MMIO Registers.</font></tt>
<br>
<br><tt><font size=2>Value is { 0x00510000 0x00001000 0x00511000 0x00001000
}.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"interrupts" property</font></tt>
<br>
<br><tt><font size=2>Standard property name: Property which specifies the
interrupt number of</font></tt>
<br><tt><font size=2>the interrupt issued by the IOC for IIC "IO Exceptions"</font></tt>
<br>
<br><tt><font size=2>Encoded as with encode-int.</font></tt>
<br>
<br><tt><font size=2>The property value consists of four bytes each representing
a specific</font></tt>
<br><tt><font size=2>value for a node, an Internal Interrupt Controller
Interrupt Service</font></tt>
<br><tt><font size=2>Routine bit mask, a class and a unit</font></tt>
<br>
<br><tt><font size=2> 0xNN3d010e (NN=node, bit 3d (61) in IIC_ISR,
class=1, unit=E for IIC_ISR</font></tt>
<br><tt><font size=2>interrupt)</font></tt>
<br>
<br><tt><font size=2>Default value is { 0i3d010e }, i = 0 for Cell Broadband
Engine processor 0,</font></tt>
<br><tt><font size=2>i = 1 for Cell Broadband Engine processor 1.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>2 "bic0" node</font></tt>
<br>
<br><tt><font size=2>The Bus Interface Controller (BIC) 0 node describes
the address range of</font></tt>
<br><tt><font size=2>MMIO register space controlling the BIC0. Besides
the standard properties</font></tt>
<br><tt><font size=2>the following property is available.</font></tt>
<br>
<br><tt><font size=2>"reg" property</font></tt>
<br>
<br><tt><font size=2>Default property name: Property to specify the MMIO
offset of the BIC0,</font></tt>
<br><tt><font size=2>which is one set of registers representing an <
offset, size > pair.</font></tt>
<br>
<br><tt><font size=2>prop-encoded-array: Encoded as with encode-phys for
the offset value,</font></tt>
<br><tt><font size=2>encode-int for the size.</font></tt>
<br>
<br><tt><font size=2>Value is { 0x00512000 0x00001000 }</font></tt>
<br>
<br><tt><font size=2>3 "bic1" node</font></tt>
<br>
<br>
<br><tt><font size=2>The Bus Interface Controller (BIC) 1 node describes
the address range of</font></tt>
<br><tt><font size=2>MMIO register space controlling the BIC1.</font></tt>
<br>
<br><tt><font size=2>"reg" property</font></tt>
<br>
<br><tt><font size=2>Default property name: Property to specify the MMIO
offset of the BIC1,</font></tt>
<br><tt><font size=2>which is one set of registers representing an <
offset, size > pair.</font></tt>
<br>
<br><tt><font size=2>prop-encoded-array: Encoded as with encode-phys for
the offset value,</font></tt>
<br><tt><font size=2>encode-int for the size.</font></tt>
<br>
<br><tt><font size=2> Value is { 0x00513000 0x00001000 }</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>4 "mic-tm" node</font></tt>
<br>
<br>
<br><tt><font size=2>The "mic-tm" node represents the Memory
Interface Controller (MIC) in the</font></tt>
<br><tt><font size=2>device tree. The main property value is the address
range of MMIO register</font></tt>
<br><tt><font size=2>space controlling the MIC.</font></tt>
<br>
<br><tt><font size=2>"reg" property</font></tt>
<br>
<br><tt><font size=2>Default property name: Property to specify the MMIO
offset of the BIC1,</font></tt>
<br><tt><font size=2>which is one set of registers representing an <
offset, size > pair.</font></tt>
<br>
<br><tt><font size=2>prop-encoded-array: Encoded as with encode-phys for
the offset value,</font></tt>
<br><tt><font size=2>encode-int for the size.</font></tt>
<br>
<br><tt><font size=2>Value is { 0x0050a000 0x00001000 }.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>5 "pervasive" node</font></tt>
<br>
<br>
<br><tt><font size=2>The pervasive node represents the 'Pervasive MMIO
Registers' in the device</font></tt>
<br><tt><font size=2>tree (i.e. Pervasive Monitor, Power Management and
Thermal Management</font></tt>
<br><tt><font size=2>described in the Cell/B.E. public register spec. The
main property value is</font></tt>
<br><tt><font size=2>the address range of MMIO register space controlling
the pervasive unit</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"reg" property</font></tt>
<br>
<br><tt><font size=2>Default property name: Property to specify the MMIO
offset of the BIC1,</font></tt>
<br><tt><font size=2>which is one set of registers representing an <
offset, size > pair.</font></tt>
<br>
<br><tt><font size=2>prop-encoded-array: Encoded as with encode-phys for
the offset value,</font></tt>
<br><tt><font size=2>encode-int for the size.</font></tt>
<br>
<br><tt><font size=2>Value is { 0x00509000 0x00001000 }.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"ppe-throttle-temp" property</font></tt>
<br>
<br><tt><font size=2>property name: Property to specify the minimum temperature
the PPE is</font></tt>
<br><tt><font size=2>throttled.</font></tt>
<br>
<br><tt><font size=2>Temperature in øC, encoded as with encode-int.</font></tt>
<br>
<br><tt><font size=2>Default value is { 0x65 } for 101øC</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"ppe-end-throttle-temp" property</font></tt>
<br>
<br><tt><font size=2>Standard property name: Property to specify the temperature
below the PPE</font></tt>
<br><tt><font size=2>throttling is exited.</font></tt>
<br>
<br><tt><font size=2>Temperature in øC, encoded as with encode-int.</font></tt>
<br>
<br><tt><font size=2>Default value is { 0x5b } for 91øC</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"ppe-full-throttle-temp" property</font></tt>
<br>
<br><tt><font size=2>property name: Property to specify the minimum
temperature the PPE is</font></tt>
<br><tt><font size=2>stopped.</font></tt>
<br>
<br><tt><font size=2>Temperature in øC, encoded as with encode-int.</font></tt>
<br>
<br><tt><font size=2>Default value is { 0x7f } for 127øC</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"spe-throttle-temp" property</font></tt>
<br>
<br><tt><font size=2>property name: : Property to specify the minimum
temperature the SPEs are</font></tt>
<br><tt><font size=2>throttled.</font></tt>
<br>
<br><tt><font size=2>Temperature in øC, encoded as with encode-int.</font></tt>
<br>
<br><tt><font size=2>Default value is { 0x65 } for 101øC</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"spe-end-throttle-temp" property</font></tt>
<br>
<br><tt><font size=2>property name: : Property to specify the temperature
below the SPEs</font></tt>
<br><tt><font size=2>throttling is exited.</font></tt>
<br>
<br><tt><font size=2>Temperature in øC, encoded as with encode-int.</font></tt>
<br>
<br><tt><font size=2>Default value is { 0x5b } for 91øC</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"spe-full-throttle-temp" property</font></tt>
<br>
<br><tt><font size=2>property name: Property to specify the minimum temperature
the PPE is</font></tt>
<br><tt><font size=2>stopped.</font></tt>
<br>
<br><tt><font size=2>Temperature in øC, encoded as with encode-int.</font></tt>
<br>
<br><tt><font size=2>Default value is { 0x6f } for 111øC</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>6 "ppe-mmio" node</font></tt>
<br>
<br>
<br><tt><font size=2>The "ppe-mmio" node represents the PowerPC
Processing Element (PPE) in the</font></tt>
<br><tt><font size=2>device tree. The main property is the address range
of MMIO register space</font></tt>
<br><tt><font size=2>controlling the PPE part of the Cell Broadband Engine
processor.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"reg" property</font></tt>
<br>
<br><tt><font size=2>Standard property name: Property to specify the MMIO
offset of the mic.</font></tt>
<br>
<br><tt><font size=2>prop-encoded-array: Encoded as with encode-phys for
the offset, encode-int</font></tt>
<br><tt><font size=2>for the size.</font></tt>
<br>
<br><tt><font size=2>Default value is { 0x00500000 0x00001000 }</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>7 "interrupt-controller" node</font></tt>
<br>
<br>
<br><tt><font size=2>The Cell Broadband Engine Architecture processor contains
an Internal</font></tt>
<br><tt><font size=2>Interrupt Controller (IIC), which is handling all
the interrupts from the</font></tt>
<br><tt><font size=2>PPE, the SPE and the connected IO.</font></tt>
<br>
<br><tt><font size=2>"reg" property</font></tt>
<br>
<br><tt><font size=2>Standard property name: Property to specify the MMIO
offset of the IIC, one</font></tt>
<br><tt><font size=2>range for each of the two threads contained in each
PPE and one range for</font></tt>
<br><tt><font size=2>the common MMIO.</font></tt>
<br>
<br><tt><font size=2>prop-encoded-array: Consisting of six 32-bit values.
The values form three</font></tt>
<br><tt><font size=2>< offset,length > pairs of the denoted space
encoded as with encode-phys</font></tt>
<br><tt><font size=2>for the offsets and encode-int for the sizes</font></tt>
<br>
<br><tt><font size=2> 1. for MMIO space of thread one</font></tt>
<br>
<br><tt><font size=2> 2. for MMIO space of thread two</font></tt>
<br>
<br><tt><font size=2> 3. for MMIO space of the common PPE MMIO
space.</font></tt>
<br>
<br><tt><font size=2>Value is</font></tt>
<br><tt><font size=2>{ 0x00508400 0x00000020 0x00508420 0x00000020 0x00508000
0x00001000 }.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"compatible" property</font></tt>
<br>
<br><tt><font size=2>property name: Property to specify the compatiblity
of this interrupt</font></tt>
<br><tt><font size=2>controller.</font></tt>
<br>
<br><tt><font size=2>Encoded as with encode-string.</font></tt>
<br>
<br><tt><font size=2>Default values is { "IBM,CBEA-Internal-Interrupt-Controller"
}.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"interrupt-controller" property</font></tt>
<br>
<br><tt><font size=2>property name: Property to specify that this node
is an interrupt</font></tt>
<br><tt><font size=2>controller.</font></tt>
<br>
<br><tt><font size=2>The mere presence of this property denotes the current
node being an</font></tt>
<br><tt><font size=2>interrupt controller.</font></tt>
<br>
<br><tt><font size=2>Zero length property.</font></tt>
<br>
<br><tt><font size=2>The value is { }.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"#interrupt-cells" property</font></tt>
<br>
<br><tt><font size=2>Standard property name: Property to specify the number
of interrupt cells.</font></tt>
<br>
<br><tt><font size=2>Encoded as with encode-int.</font></tt>
<br>
<br><tt><font size=2>Default value is { 0x1 }.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"ibm,interrupt-server-ranges" property</font></tt>
<br>
<br><tt><font size=2>property name: Property to specify the threads handled
by this interrupt</font></tt>
<br><tt><font size=2>controller.</font></tt>
<br>
<br><tt><font size=2>Array of threads, encoded as with encode-int.</font></tt>
<br>
<br><tt><font size=2>Default values for</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>|Cell Broadband Engine |Property Value
|</font></tt>
<br><tt><font size=2>|Architecture processor # |
|</font></tt>
<br><tt><font size=2>|0
|{ 0x00000000 0x00000001 }|</font></tt>
<br><tt><font size=2>|1
|{ 0x00000000 0x00000001 }|</font></tt>
<br>
<br>
<br><tt><font size=2>8 "spe" nodes</font></tt>
<br>
<br>
<br><tt><font size=2>The Cell Broadband Engine Architecture processor contains
eight SPEs, each</font></tt>
<br><tt><font size=2>consisting of an SPU, 256kB local store and a Memory
Flow Controller (MFC).</font></tt>
<br><tt><font size=2>The SPEs are connected to the EIB (Element Interconnect
Bus) ring. The</font></tt>
<br><tt><font size=2>access to the internal devices is done via MMIO reads,
with a fixed offset</font></tt>
<br><tt><font size=2>to the Cell Broadband Engine processor base address.</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>"reg" property</font></tt>
<br>
<br><tt><font size=2>Standard property name: Specifies the MMIO offset
and size of the SPEs</font></tt>
<br><tt><font size=2>Local Storage, Problem-State, Privilege 2 Area and
Privilege 1 Area.</font></tt>
<br>
<br><tt><font size=2>prop-encoded array: Encoded as four < offset, length
> pairs per SPE</font></tt>
<br><tt><font size=2>encoded as with encode-phys for the offsets, encode-int
for the size. The</font></tt>
<br><tt><font size=2>pairs define the following SPE units:</font></tt>
<br>
<br><tt><font size=2> 1. Local Store (LS)</font></tt>
<br>
<br><tt><font size=2> 2. Problem State MMIO Registers</font></tt>
<br>
<br><tt><font size=2> 3. Privilege State 2 MMIO Registers</font></tt>
<br>
<br><tt><font size=2> 4. Privilege State 1 MMIO Registers</font></tt>
<br>
<br><tt><font size=2>The property exists once in each spe node.</font></tt>
<br>
<br><tt><font size=2>Default values for SPE</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>|# |Property Value
|</font></tt>
<br><tt><font size=2>|spe@0 |{ 0x00000000 0x00040000
0x00040000 |</font></tt>
<br><tt><font size=2>| |0x00020000
|</font></tt>
<br><tt><font size=2>| |0x00060000
0x00020000 0x00400000 |</font></tt>
<br><tt><font size=2>| |0x00002000
}
|</font></tt>
<br><tt><font size=2>|spe@80000 |{ 0x00080000 0x00040000 0x000c0000
|</font></tt>
<br><tt><font size=2>| |0x00020000
|</font></tt>
<br><tt><font size=2>| |0x000e0000
0x00020000 0x00402000 |</font></tt>
<br><tt><font size=2>| |0x00002000
}
|</font></tt>
<br><tt><font size=2>|spe@100000 |{ 0x00100000 0x00040000 0x00140000
|</font></tt>
<br><tt><font size=2>| |0x00020000
|</font></tt>
<br><tt><font size=2>| |0x00160000
0x00020000 0x00404000 |</font></tt>
<br><tt><font size=2>| |0x00002000
}
|</font></tt>
<br><tt><font size=2>|spe@180000 |{ 0x00180000 0x00040000 0x001c0000
|</font></tt>
<br><tt><font size=2>| |0x00020000
|</font></tt>
<br><tt><font size=2>| |0x001e0000
0x00020000 0x00406000 |</font></tt>
<br><tt><font size=2>| |0x00002000
}
|</font></tt>
<br><tt><font size=2>|spe@200000 |{ 0x00200000 0x00040000 0x00240000
|</font></tt>
<br><tt><font size=2>| |0x00020000
|</font></tt>
<br><tt><font size=2>| |0x00260000
0x00020000 0x00408000 |</font></tt>
<br><tt><font size=2>| |0x00002000
}
|</font></tt>
<br><tt><font size=2>|spe@280000 |{ 0x00280000 0x00040000 0x002c0000
|</font></tt>
<br><tt><font size=2>| |0x00020000
|</font></tt>
<br><tt><font size=2>| |0x002e0000
0x00020000 0x0040a000 |</font></tt>
<br><tt><font size=2>| |0x00002000
}
|</font></tt>
<br><tt><font size=2>|spe@300000 |{ 0x00280000 0x00040000 0x002c0000
|</font></tt>
<br><tt><font size=2>| |0x00020000
|</font></tt>
<br><tt><font size=2>| |0x002e0000
0x00020000 0x0040a000 |</font></tt>
<br><tt><font size=2>| |0x00002000
}
|</font></tt>
<br><tt><font size=2>|spe@380000 |{ 0x00380000 0x00040000 0x003c0000
|</font></tt>
<br><tt><font size=2>| |0x00020000
|</font></tt>
<br><tt><font size=2>| |0x003e0000
0x00020000 0x0040e000 |</font></tt>
<br><tt><font size=2>| |0x00002000
}
|</font></tt>
<br>
<br>
<br><tt><font size=2>"interrupts" property</font></tt>
<br>
<br><tt><font size=2>Standard property name: Property to specify the interrupt
numbers of the</font></tt>
<br><tt><font size=2>interrupts issued by SPE.</font></tt>
<br>
<br><tt><font size=2>prop-encoded array: List of interrupt numbers issued
by the SPE. Each value</font></tt>
<br><tt><font size=2>in the list is encoded as with encode-int.</font></tt>
<br>
<br><tt><font size=2>The property exists once in each spe node.</font></tt>
<br>
<br><tt><font size=2>Default values for SPEs are</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>|# |Property Value
|</font></tt>
<br><tt><font size=2>|spe@0 |{ 0x4, 0x104, 0x204 }
|</font></tt>
<br><tt><font size=2>|spe@80000 |{ 0x7, 0x107, 0x207 }
|</font></tt>
<br><tt><font size=2>|spe@100000 |{ 0x3, 0x103, 0x203 }
|</font></tt>
<br><tt><font size=2>|spe@180000 |{ 0x8, 0x108, 0x208 }
|</font></tt>
<br><tt><font size=2>|spe@200000 |{ 0x2, 0x102, 0x202 }
|</font></tt>
<br><tt><font size=2>|spe@280000 |{ 0x9, 0x109, 0x209 }
|</font></tt>
<br><tt><font size=2>|spe@300000 |{0x1, 0x101, 0x201 }
|</font></tt>
<br><tt><font size=2>|spe@380000 |{0xa, 0x10a, 0x20a }
|</font></tt>
<br>
<br>
<br><tt><font size=2>"vicinity" property</font></tt>
<br>
<br><tt><font size=2>property name: Specifies the direct neighbouring componentes
on the EIB</font></tt>
<br><tt><font size=2>ring related to each SPE.</font></tt>
<br>
<br><tt><font size=2>prop-encoded array: Pairs of phandles ( < phandle,
phandle >) of the</font></tt>
<br><tt><font size=2>neighbouring nodes, each phandle is encoded as with
encode-int.</font></tt>
<br>
<br><tt><font size=2>The property exists once in each spe node.</font></tt>
<br>
<br><tt><font size=2>Default values for SPEs</font></tt>
<br>
<br>
<br>
<br><tt><font size=2>|# |Property Value
|</font></tt>
<br><tt><font size=2>|spe@0 |{ phandle(mic-tm, SPE
3) } |</font></tt>
<br><tt><font size=2>|spe@80000 |{ phandle(mic-tm, SPE 2) }
|</font></tt>
<br><tt><font size=2>|spe@100000 |{ phandle(SPE 0, SPE 4) }
|</font></tt>
<br><tt><font size=2>|spe@180000 |{ phandle(SPE 1, SPE 5) }
|</font></tt>
<br><tt><font size=2>|spe@200000 |{ phandle(SPE 2, SPE 6) }
|</font></tt>
<br><tt><font size=2>|spe@280000 |{ phandle(SPE 3, SPE 7) }
|</font></tt>
<br><tt><font size=2>|spe@300000 |{ phandle(SPE 4, BIC0) }
|</font></tt>
<br><tt><font size=2>|spe@380000 |{ phandle(SPE 5, BIC0) }
|</font></tt>
<br>
<br>
<br><tt><font size=2>Appendix A - Bibliography</font></tt>
<br>
<br><tt><font size=2>This section lists documents which were referenced
in this specification or</font></tt>
<br><tt><font size=2>which provide additional information,
and some useful information for</font></tt>
<br><tt><font size=2>obtaining these documents. Referenced documents are
listed below. When any</font></tt>
<br><tt><font size=2>of the following standards are superseded by
an approved revision, the</font></tt>
<br><tt><font size=2>revision shall apply.</font></tt>
<br>
<br><tt><font size=2> 1. IEEE 1275, IEEE Standard for Boot
(Initialization Configuration)</font></tt>
<br><tt><font size=2> Firmware: Core Requirements and
Practices</font></tt>
<br>
<br><tt><font size=2> IEEE part number DS02683, ISBN
1-55937-426-8</font></tt>
<br>
<br><tt><font size=2> 2. PowerPC Processor binding to:
IEEE 1275, IEEE Standard for Boot</font></tt>
<br><tt><font size=2> (Initialization Configuration)
Firmware: Core Requirements and</font></tt>
<br><tt><font size=2> Practices</font></tt>
<br>
<br><tt><font size=2> 3. Power.org Standard for
Power Architecture Platform Requirements</font></tt>
<br><tt><font size=2> (Workstation, Server) Version
2.2, 9th Oct 2007</font></tt>
<br>