<br><tt><font size=3>Dear Subscribers and Readers,<br>
<br>
this is a reminder for review. Feedback appreciated!</font></tt>
<br><tt><font size=3>For convenience I removed the disclaimer etc.</font></tt>
<br>
<br><tt><font size=3>On dec 5th I posted our (complete) draft version of
the Cell/B.E. device tree documentation.<br>
See also in devicetree-discuss Digest, Vol 6, Issue 1.</font></tt>
<br>
<br><tt><font size=3>Goal of these review should be to finally establish
the document as Power.org <br>
PAPR Binding for the Cell/B.E. processor.<br>
<br>
Please review and give us feedback.<br>
<br>
Thanks.</font></tt>
<br><tt><font size=3>_________________________________<br>
<br>
DRAFT Power.org Standard for the Cell Broadband Engine architecture device<br>
tree<br>
</font></tt>
<br><tt><font size=3>Table of Contents<br>
<br>
<br>
<br>
1 Overview 5<br>
<br>
1.1 Scope 5<br>
<br>
1.2 Purpose 5<br>
<br>
2 Terminology 5<br>
<br>
2.1 Definitions 5<br>
<br>
2.2 Abbreviations 5<br>
<br>
2.3 Acronyms 5<br>
<br>
3 Introduction 6<br>
<br>
4 The Cell Broadband Engine architecture processor
representation in<br>
the device tree 7<br>
<br>
4.1 "be" node 7<br>
<br>
4.1.1 ioc node 10<br>
<br>
4.1.2 "bic0" node 11<br>
<br>
4.1.3 "bic1" node 11<br>
<br>
4.1.4 "mic-tm" node 12<br>
<br>
4.1.5 "pervasive" node 12<br>
<br>
4.1.6 "ppe-mmio" node 14<br>
<br>
4.1.7 "interrupt-controller" node 15<br>
<br>
4.1.8 "spe" nodes 16<br>
<br>
<br>
DRAFT Power.org Standard for the Cell Broadband Engine architecture device<br>
tree<br>
<br>
Overview<br>
<br>
<br>
1 Scope<br>
<br>
<br>
This document is intended to apply the Power.org
Standard for Power<br>
Architecture Platform Requirements (Workstation,
Server) PAPR on<br>
Cell Broadband Engine architecture compliant processors.
This<br>
encompasses requirements therein and additional requirements
for<br>
device tree nodes and properties pertaining to Cell
Broadband Engine<br>
architecture compliant processors.<br>
<br>
2 Purpose<br>
<br>
<br>
This document is intended to indicate the architectural
option and<br>
feature set of Cell Broadband Engine architecture
processors to<br>
software via Open Firmware (OF).<br>
<br>
Terminology<br>
<br>
<br>
This document uses definitions, abbreviations
and acronyms as<br>
indicated below or in the PAPR specification
[3].<br>
<br>
1 Definitions<br>
<br>
<br>
Device Tree: Open Firmware data structure representing
the set of<br>
devices
attached to a system. See [1] for details.<br>
<br>
2 Abbreviations<br>
<br>
<br>
Define key abbreviations here (use "paragraph"
plus tab), such as<br>
<br>
l.t.s.f.l.r. Leaving this section for
later revisions of this<br>
document - to be removed if not used !!!!!!!!!!!!<br>
<br>
3 Acronyms<br>
<br>
<br>
Define key acronyms here (use "paragraph"
style with tabs"), such as<br>
<br>
EIB Element Interconnect
Bus<br>
<br>
IIC Internal Interrupt
Controller<br>
<br>
IOC Input Output Controller<br>
<br>
MMIO Memory Mapped Input
Output<br>
<br>
OF Open Firmware
(see [1]).<br>
<br>
PPE PowerPC Processing
Element<br>
<br>
SPE Synergistic Processing
Element<br>
<br>
<br>
<br>
Introduction<br>
<br>
<br>
The specific goals of this specification are as follows:<br>
<br>
. To provide the address map for the
components in a Cell<br>
Broadband Engine Architecture
processor. Subcomponent address<br>
information is detected by the
OF and passed to the OS in the<br>
device tree.<br>
<br>
<br>
. To build upon the OF boot environment
defined in IEEE 1275,<br>
IEEE Standard for Boot (Initialization
Configuration) Firmware:<br>
Core Requirements and Practices.<br>
<br>
<br>
. To provide device tree nodes and
property values necessary for<br>
access to and configuration
of the Cell Broadband Engine<br>
Architecture processor subcomponents.<br>
<br>
The Cell Broadband Engine architecture processors are implemented as<br>
systems on a chip. Besides a PowerPC processor it contains eight<br>
Synergistic Processing Elements (SPEs) in addition. Each SPE has access
to<br>
256kB of associated local store. All logic of the non-processor part is<br>
accessed via MMIO. Mapping and structure of the MMIO space are described<br>
with the "be" node. A nodes' unit address is the MMIO address
of that<br>
particular BE. The "be" node is located in the device tree as
child of the<br>
root node '/'.<br>
<br>
The Cell Broadband Engine architecture processor representation
in the<br>
device tree<br>
<br>
<br>
The following contents are outlined according to the hierarchy of the<br>
components in the sub-tree containing the components of the Cell Broadband<br>
Engine processor.<br>
<br>
All device tree nodes detailed below contain a "name" property
in addition<br>
to the mentioned properties as follows<br>
<br>
. Specifies the name of the node<br>
<br>
<br>
. Encoded as with encode-string<br>
<br>
<br>
. Default is the name of the node<br>
<br>
<br>
Throughout the description below
the notation<br>
phandle(<expression>)
is used to retrieve the phandle of a<br>
node. A phandle of a device
tree node is the cell-sized datum<br>
identifying the particular device
tree node.<br>
<br>
1 "be" node<br>
<br>
<br>
The "be" node contains a set of properties and sub-nodes, which
describe<br>
the structure of a Cell Broadband Engine Architecture processor. All the<br>
devices are contained, except the Power PC processor core nodes, which
are<br>
located under the "/cpus" path according to the PowerPC Processor
binding<br>
to the IEEE 1275 standard.<br>
<br>
"reg" property<br>
<br>
Standard property name specifying
the < address, size > pair of<br>
the Cell Broadband Engine processor's
MMIO mapped registers.<br>
<br>
<br>
Prop-encoded array: Encoded
as with encode-phys for the<br>
address. The size part is encoded
with two encode-ints.<br>
<br>
<br>
The array consists of four 32-bit
values. Value one and two in<br>
this array correspond to the
64-bit address value the the Cell<br>
Broadband Engine Architecture
processor is mapped into. Value<br>
three and four correspond to
the 64-bit size. Both pairs<br>
represent the < address,
size > pair of MMIO mapped registers<br>
in the Cell Broadband Engine
processor's MMIO mapped register<br>
space.<br>
<br>
<br>
Default value is { 0x00000iii
0x00000000 0x00000000 0x000800000<br>
}, where iii is the offset defined
by the hardware settings.<br>
<br>
"ranges" property<br>
<br>
Standard property name which
specifies the mapping of the child<br>
of the "be" node within
the "be" nodes' parent address space<br>
using the < child, parent,
size > triple.<br>
<br>
<br>
Prop-encoded array: Encoded
as with encode-int for the childs<br>
range, encode-phys for the parents
range and encode-int for the<br>
size.<br>
<br>
<br>
The array consists of four 32-bit
values. Value one in this<br>
array corresponds to the 32-bit
child address encoded as with<br>
encode-int. Value two and three
correspond to the 64-bit parent<br>
address encoded as with encode-phys.
Value three in this array<br>
corresponds to the 32-bit size.<br>
<br>
<br>
Default value is { 0x00000000
0x00000iii 0x00000000 0x00080000<br>
}, mapping address 0 of child
to 0x00000iii 00000000.<br>
<br>
"device-type" property<br>
<br>
<br>
Standard property name which
specifies the type of the node.<br>
<br>
<br>
Encoded as with encode-string.<br>
<br>
<br>
Default value is { "be"
}.<br>
<br>
<br>
<br>
"model" property<br>
<br>
<br>
property name: Specifies model
of node.<br>
<br>
<br>
Encoded as with encode-string.<br>
<br>
<br>
Default value is { "IBM,CBEA"
}.<br>
<br>
<br>
<br>
"ibm,dt-version" property<br>
<br>
property name: Specifies the current device tree version number. The<br>
version number format is major.minor.<br>
<br>
Whenever the device tree is changed or extended in a way that OS changes<br>
are required the major version is changed.<br>
<br>
The minor version is changed when at least one new property is added or<br>
removed.<br>
<br>
Encoded as with encode-string<br>
<br>
The default value is { 1.1 }<br>
<br>
<br>
<br>
"#address-cells" property<br>
<br>
<br>
property name which specifies the number of address cells for child nodes<br>
to the current node.<br>
<br>
<br>
Encoded as with encode-int.<br>
<br>
<br>
Default value is { 1 }<br>
<br>
<br>
<br>
"#size-cells" property<br>
<br>
Standard property name which specifies the number of size cells for child<br>
nodes to the current node.<br>
<br>
Encoded as with encode-int.<br>
<br>
Default value is { 1 }<br>
<br>
<br>
<br>
"ibm,associativity" property<br>
<br>
property name: Property to define the associativity domains for this<br>
resource.<br>
See Power Architecture Platform Requirements (PAPR) [3], Sections<br>
14.11.2.2, 15.2, 15.3, 18.3 and C.6.2.2 for details on this property.<br>
<br>
Set values to { 4 0x00000000, 0x00000000, 0x0000000i, 0x0000000i }; i =
0<br>
for associativity to Cell Broadband Engine processor 0, i = 1 for<br>
associativity to Cell Broadband Engine processor 1.<br>
<br>
<br>
<br>
"interrupt-parent" property<br>
<br>
property name: Property that specifies the interrupt handler responsible<br>
for this node.<br>
<br>
The value represents a phandle of the interrupt handler node, encoded as<br>
with encode-int.<br>
<br>
Default value is { phandle( my-self/interrupt-controller) }<br>
<br>
<br>
<br>
"cpus" property<br>
<br>
property name: Porperty to specify the PPE component of the Cell Broadband<br>
Engine architecture processor chip.<br>
<br>
phandle of the cpu node, encoded as with encode-int.<br>
<br>
Default value is { phandle(/cpus/PowerPC,BE@i) }; i = 0 for Cell Broadband<br>
Engine Architecture processor 0, i = 1 for Cell Broadband Engine<br>
Architecture processor 1.<br>
<br>
1 ioc node<br>
<br>
<br>
The Input/Output Controller (IOC) node contains among others the properties<br>
specifying the address range of MMIO register space controlling the IOC.<br>
<br>
"reg" property<br>
<br>
Default property name: Property to specify the MMIO offset of the IOC,<br>
which are two sets of registers each represented by an < offset, size
><br>
pair.<br>
<br>
prop-encoded-array: Encoded as with encode-phys for the offset values,<br>
encode-int for the size values.<br>
<br>
The array consists of four 32-bit values to represent two < offset,
size ><br>
pairs. Value one in this array corresponds to the first offset value within<br>
the child address space, encoded as with encode-phys. Value two corresponds<br>
to the size, encoded as with encode-int. Value three in this array<br>
corresponds to the second offset value, value four to the second size.<br>
<br>
Default value is { 0x00510000 0x00001000 0x00511000 0x00001000 }.<br>
<br>
<br>
<br>
"device_type" property<br>
<br>
Standard property name: Specify the type of this node<br>
<br>
Encoded as with encode-string<br>
<br>
Default value is { "ioc" }<br>
<br>
<br>
<br>
"interrupts" property<br>
<br>
Standard property name: Property which specifies the interrupt number of<br>
the interrupt issued by the IOC for IIC "IO Exceptions"<br>
<br>
Encoded as with encode-int.<br>
<br>
The property value consists of four bytes each representing a specific<br>
value for a node, an Internal Interrupt Controller Interrupt Service<br>
Routine bit mask, a class and a unit<br>
<br>
0xNN3d010e (NN=node, bit 3d (61) in IIC_ISR, class=1, unit=E for IIC_ISR<br>
interrupt)<br>
<br>
Default value is { 0i3d010e }, i = 0 for Cell Broadband Engine processor
0,<br>
i = 1 for Cell Broadband Engine processor 1.<br>
<br>
<br>
<br>
2 "bic0" node<br>
<br>
<br>
The Bus Interface Controller (BIC) 0 node describes the address range of<br>
MMIO register space controlling the BIC0.<br>
<br>
"reg" property<br>
<br>
Default property name: Property to specify the MMIO offset of the BIC0,<br>
which is one set of registers representing an < offset, size > pair.<br>
<br>
prop-encoded-array: Encoded as with encode-phys for the offset value,<br>
encode-int for the size.<br>
<br>
Default value is { 0x00512000 0x00001000 }<br>
<br>
<br>
<br>
"device_type" property<br>
<br>
Standard property name: Property to specify the type of this node.<br>
<br>
Encoded as with encode-string.<br>
<br>
Default value is { "bic0" }.<br>
<br>
<br>
<br>
3 "bic1" node<br>
<br>
<br>
The Bus Interface Controller (BIC) 1 node describes the address range of<br>
MMIO register space controlling the BIC1.<br>
<br>
"reg" property<br>
<br>
Default property name: Property to specify the MMIO offset of the BIC1,<br>
which is one set of registers representing an < offset, size > pair.<br>
<br>
prop-encoded-array: Encoded as with encode-phys for the offset value,<br>
encode-int for the size.<br>
<br>
Default value is { 0x00513000 0x00001000 }<br>
<br>
<br>
<br>
"device_type" property<br>
<br>
Standard property name: Property to pecify the type of this node.<br>
<br>
Encoded as with encode-string.<br>
<br>
Default value is { "bic1" }.<br>
<br>
<br>
<br>
4 "mic-tm" node<br>
<br>
<br>
The "mic-tm" node represents the Memory Interface Controller
(MIC) in the<br>
device tree. The main property value is the address range of MMIO register<br>
space controlling the MIC.<br>
<br>
"reg" property<br>
<br>
Default property name: Property to specify the MMIO offset of the BIC1,<br>
which is one set of registers representing an < offset, size > pair.<br>
<br>
prop-encoded-array: Encoded as with encode-phys for the offset value,<br>
encode-int for the size.<br>
<br>
Default value is { 0x0050a000 0x00001000 }.<br>
<br>
<br>
<br>
"device_type" property<br>
<br>
Standard property name: Specify the type of this node.<br>
<br>
Encoded as with encode-string.<br>
<br>
Default value is { "mic-tm" }.<br>
<br>
<br>
<br>
5 "pervasive" node<br>
<br>
<br>
The pervasive node node represents the pervasive unit in the device
tree.<br>
T>he main property value is the address range of MMIO register space<br>
controlling the pervasive unit.<br>
<br>
"reg" property<br>
<br>
Default property name: Property to specify the MMIO offset of the BIC1,<br>
which is one set of registers representing an < offset, size > pair.<br>
<br>
prop-encoded-array: Encoded as with encode-phys for the offset value,<br>
encode-int for the size.<br>
<br>
Default value is { 0x00509000 0x00001000 }.<br>
<br>
<br>
<br>
"device_type" property<br>
<br>
Standard property name: Property to specify the type of this node.<br>
<br>
Encoded as with encode-string.<br>
<br>
Default value is { "pervasive" }.<br>
<br>
<br>
<br>
"ppe-throttle-temp" property<br>
<br>
property name: Property to specify the minimum temperature the PPE is<br>
throttled.<br>
<br>
Temperature in °C, encoded as with encode-int.<br>
<br>
Default value is { 0x65 } for 101°C<br>
<br>
<br>
<br>
"ppe-end-throttle-temp" property<br>
<br>
Standard property name: Property to specify the temperature below the PPE<br>
throttling is exited.<br>
<br>
Temperature in °C, encoded as with encode-int.<br>
<br>
Default value is { 0x5b } for 91°C<br>
<br>
<br>
<br>
"ppe-full-throttle-temp" property<br>
<br>
property name: Property to specify the minimum temperature the PPE
is<br>
stopped.<br>
<br>
Temperature in °C, encoded as with encode-int.<br>
<br>
Default value is { 0x7f } for 127°C<br>
<br>
<br>
<br>
"spe-throttle-temp" property<br>
<br>
property name: : Property to specify the minimum temperature the
SPEs are<br>
throttled.</font></tt>
<br><tt><font size=3><br>
Temperature in °C, encoded as with encode-int.<br>
<br>
Default value is { 0x65 } for 101°C<br>
<br>
<br>
<br>
"spe-end-throttle-temp" property<br>
<br>
property name: : Property to specify the temperature below the SPEs<br>
throttling is exited.<br>
<br>
Temperature in °C, encoded as with encode-int.<br>
<br>
Default value is { 0x5b } for 91°C<br>
<br>
<br>
<br>
"spe-full-throttle-temp" property<br>
<br>
property name: Property to specify the minimum temperature the PPE is<br>
stopped.<br>
<br>
Temperature in °C, encoded as with encode-int.<br>
<br>
Default value is { 0x6f } for 111°C<br>
<br>
<br>
<br>
6 "ppe-mmio" node<br>
<br>
<br>
The "ppe-mmio" node represents the PowerPC Processing Element
(PPE) in the<br>
device tree. The main property is the address range of MMIO register space<br>
controlling the PPE part of the Cell Broadband Engine processor.<br>
<br>
<br>
<br>
"reg" property<br>
<br>
Standard property name: Property to specify the MMIO offset of the mic.<br>
<br>
prop-encoded-array: Encoded as with encode-phys for the offset, encode-int<br>
for the size.<br>
<br>
Default value is { 0x00500000 0x00001000 }<br>
<br>
<br>
<br>
"device_type" property<br>
<br>
Standard property name: Property to specify the type of this node.<br>
<br>
Encoded as with encode-string.<br>
<br>
Default value is { "ppe-mmio" }.<br>
<br>
<br>
<br>
7 "interrupt-controller" node<br>
<br>
<br>
The Cell Broadband Engine Architecture processor contains an Internal<br>
Interrupt Controller (IIC), which is handling all the interrupts from the<br>
PPE, the SPE and the connected IO.<br>
<br>
"reg" property<br>
<br>
Standard property name: Property to specify the MMIO offset of the IIC,
one<br>
range for each of the two threads contained in each PPE and one range for<br>
the common MMIO.<br>
<br>
prop-encoded-array: Consisting of six 32-bit values. The values form three<br>
< offset,length > pairs of the denoted space encoded as with encode-phys<br>
for the offsets and encode-int for the sizes<br>
<br>
1. for MMIO space of thread one<br>
<br>
2. for MMIO space of thread two<br>
<br>
3. for MMIO space of the common PPE MMIO space.<br>
<br>
Default value is<br>
{ 0x00508400 0x00000020 0x00508420 0x00000020 0x00508000 0x00001000 }.<br>
<br>
<br>
<br>
"device_type" property<br>
<br>
Standard property name: Property to specify the type of this node.<br>
<br>
Encoded as with encode-string.<br>
<br>
Default value is { "CBEA-Internal-Interrupt-Controller" }.<br>
<br>
<br>
<br>
"compatible" property<br>
<br>
property name: Property to specify the compatiblity of this interrupt<br>
controller.<br>
<br>
Encoded as with encode-string.<br>
<br>
Default values is { "IBM,CBEA-Internal-Interrupt-Controller"
}.<br>
<br>
<br>
<br>
"interrupt-controller" property<br>
<br>
property name: Property to specify that this node is an interrupt<br>
controller.<br>
<br>
The mere presence of this property denotes the current node being an<br>
interrupt controller.<br>
<br>
Zero length property.<br>
<br>
The value is {}.<br>
<br>
<br>
<br>
"#interrupt-cells" property<br>
<br>
Standard property name: Property to specify the number of interrupt cells.<br>
<br>
Encoded as with encode-int.<br>
<br>
Default value is { 0x1 }.<br>
<br>
<br>
<br>
"ibm,interrupt-server-ranges" property<br>
<br>
property name: Property to specify the threads handled by this interrupt<br>
controller.<br>
<br>
Array of threads, encoded as with encode-int.<br>
<br>
Default values for<br>
<br>
<br>
<br>
|Cell Broadband Engine |Property Value
|<br>
|Architecture processor # |
|<br>
|0
|{ 0x00000000 0x00000001 }|<br>
|1
|{ 0x00000000 0x00000001 }|<br>
<br>
<br>
8 "spe" nodes<br>
<br>
<br>
The Cell Broadband Engine Architecture processor contains eight SPEs, each<br>
consisting of an SPU, 256kB local store and a Memory Flow Controller (MFC).<br>
The SPEs are connected to the EIB (Element Interconnect Bus) ring. The<br>
access to the internal devices is done via MMIO reads, with a fixed offset<br>
to the Cell Broadband Engine processor base address.<br>
<br>
<br>
<br>
"reg" property<br>
<br>
Standard property name: Specifies the MMIO offset and size of the SPEs<br>
Local Storage, Problem-State, Privilege 2 Area and Privilege 1 Area.<br>
<br>
prop-encoded array: Encoded as four < offset, length > pairs per
SPE<br>
encoded as with encode-phys for the offsets, encode-int for the size. The<br>
pairs define the following SPE units:<br>
<br>
1. Local Store (LS)<br>
<br>
2. Problem State MMIO Registers<br>
<br>
3. Privilege State 2 MMIO Registers<br>
<br>
4. Privilege State 1 MMIO Registers<br>
<br>
The property exists once in each spe node.<br>
<br>
Default values for SPE<br>
<br>
<br>
<br>
|# |Property Value
|<br>
|spe@0 |{ 0x00000000 0x00040000 0x00040000
|<br>
| |0x00020000
|<br>
| |0x00060000 0x00020000 0x00400000
|<br>
| |0x00002000 }
|<br>
|spe@80000 |{ 0x00080000 0x00040000 0x000c0000
|<br>
| |0x00020000
|<br>
| |0x000e0000 0x00020000 0x00402000
|<br>
| |0x00002000 }
|<br>
|spe@100000 |{ 0x00100000 0x00040000 0x00140000
|<br>
| |0x00020000
|<br>
| |0x00160000 0x00020000 0x00404000
|<br>
| |0x00002000 }
|<br>
|spe@180000 |{ 0x00180000 0x00040000 0x001c0000
|<br>
| |0x00020000
|<br>
| |0x001e0000 0x00020000 0x00406000
|<br>
| |0x00002000 }
|<br>
|spe@200000 |{ 0x00200000 0x00040000 0x00240000
|<br>
| |0x00020000
|<br>
| |0x00260000 0x00020000 0x00408000
|<br>
| |0x00002000 }
|<br>
|spe@280000 |{ 0x00280000 0x00040000 0x002c0000
|<br>
| |0x00020000
|<br>
| |0x002e0000 0x00020000 0x0040a000
|<br>
| |0x00002000 }
|<br>
|spe@300000 |{ 0x00280000 0x00040000 0x002c0000
|<br>
| |0x00020000
|<br>
| |0x002e0000 0x00020000 0x0040a000
|<br>
| |0x00002000 }
|<br>
|spe@380000 |{ 0x00380000 0x00040000 0x003c0000
|<br>
| |0x00020000
|<br>
| |0x003e0000 0x00020000 0x0040e000
|<br>
| |0x00002000 }
|<br>
<br>
<br>
"device_type" property<br>
<br>
Standard property name: Specifies the type of this node.<br>
<br>
Encoded as with encode-string.<br>
<br>
Default value is {"spe" }.<br>
<br>
<br>
<br>
"interrupts" property<br>
<br>
Standard property name: Property to specify the interrupt numbers of the<br>
interrupts issued by SPE.<br>
<br>
prop-encoded array: List of interrupt numbers issued by the SPE. Each value<br>
in the list is encoded as with encode-int.<br>
<br>
The property exists once in each spe node.<br>
<br>
Default values for SPEs are<br>
<br>
<br>
<br>
|# |Property Value
|<br>
|spe@0 |{ 0x4, 0x104, 0x204 }
|<br>
|spe@80000 |{ 0x7, 0x107, 0x207 }
|<br>
|spe@100000 |{ 0x3, 0x103, 0x203 }
|<br>
|spe@180000 |{ 0x8, 0x108, 0x208 }
|<br>
|spe@200000 |{ 0x2, 0x102, 0x202 }
|<br>
|spe@280000 |{ 0x9, 0x109, 0x209 }
|<br>
|spe@300000 |{0x1, 0x101, 0x201 }
|<br>
|spe@380000 |{0xa, 0x10a, 0x20a }
|<br>
<br>
<br>
"vicinity" property<br>
<br>
property name: Specifies the direct neighbouring componentes on the EIB<br>
ring related to each SPE.<br>
<br>
prop-encoded array: Pairs of phandles ( < phandle, phandle >) of
the<br>
neighbouring nodes, each phandle is encoded as with encode-int.<br>
<br>
The property exists once in each spe node.<br>
<br>
Default values for SPEs<br>
<br>
<br>
<br>
|# |Property Value
|<br>
|spe@0 |{ phandle(mic-tm, SPE 3) }
|<br>
|spe@80000 |{ phandle(mic-tm, SPE 2) }
|<br>
|spe@100000 |{ phandle(SPE 0, SPE 4) }
|<br>
|spe@180000 |{ phandle(SPE 1, SPE 5) }
|<br>
|spe@200000 |{ phandle(SPE 2, SPE 6) }
|<br>
|spe@280000 |{ phandle(SPE 3, SPE 7) }
|<br>
|spe@300000 |{ phandle(SPE 4, BIC0) }
|<br>
|spe@380000 |{ phandle(SPE 5, BIC0) }
|<br>
<br>
<br>
"physical-id" property<br>
<br>
property name: Property to specify the physical id of an SPE.<br>
<br>
Default values for the physical id is encoded as with encode-int.<br>
<br>
The property exists once in each spe node.<br>
<br>
<br>
<br>
|# |Property Value
|<br>
|spe@0 |{ 0 }
|<br>
|spe@80000 |{ 1 }
|<br>
|spe@100000 |{ 2 }
|<br>
|spe@180000 |{ 3 }
|<br>
|spe@200000 |{ 4 }
|<br>
|spe@280000 |{ 5 }
|<br>
|spe@300000 |{ 6 }
|<br>
|spe@380000 |{ 7 }
|<br>
Appendix A - Bibliography<br>
<br>
This section lists documents which were referenced in this specification
or<br>
which provide additional information, and some
useful information for<br>
obtaining these documents. Referenced documents are listed below. When
any<br>
of the following standards are superseded by an approved
revision, the<br>
revision shall apply.<br>
<br>
1. IEEE 1275, IEEE Standard for Boot (Initialization Configuration)<br>
Firmware: Core Requirements and Practices<br>
<br>
IEEE part number DS02683, ISBN 1-55937-426-8<br>
<br>
2. PowerPC Processor binding to: IEEE 1275, IEEE
Standard for Boot<br>
(Initialization Configuration) Firmware:
Core Requirements and<br>
Practices<br>
<br>
3. Power.org Standard for Power Architecture
Platform Requirements<br>
(Workstation, Server) Version 2.2, 9th Oct 2007</font></tt>
<br><font size=2 face="sans-serif"><br>
</font><font size=1 face="Arial">Mit freundlichen Grüßen / Kind regards</font><font size=2 face="Arial"><b><br>
Christian Rund</b></font><font size=3> </font>
<table>
<tr>
<td colspan=4><font size=1 color=#0060a0 face="Arial">Engineer in Development,
SLOF, directCell, Systems Management</font>
<tr>
<td colspan=4><font size=1 color=#0060a0 face="Arial">IBM Systems &
Technology Group, Integrated Systems Development</font>
<tr>
<td colspan=4><font size=1 color=#0060a0 face="Arial">Open Systems Firmware
Development</font>
<tr>
<td colspan=4>
<hr>
<tr>
<td><font size=1 color=#0060a0 face="Arial">Phone:</font>
<td><font size=1 color=#0060a0 face="Arial">+49-7031-16-3235</font>
<td><font size=1 color=#0060a0 face="Arial"> IBM Deutschland</font>
<td rowspan=4>
<div align=right><img src=cid:_1_06FE8AA806FE86EC004D3F4EC1257521></div>
<tr>
<td><font size=1 color=#0060a0 face="Arial">E-Mail:</font>
<td><font size=1 color=#0060a0 face="Arial">Christian.Rund@de.ibm.com</font>
<td><font size=1 color=#0060a0 face="Arial"> Schoenaicher Str. 220</font>
<tr>
<td>
<td>
<td><font size=1 color=#0060a0 face="Arial"> 71032 Boeblingen</font>
<tr>
<td><font size=1 color=#0060a0 face="Arial"> </font>
<td><font size=1 color=#0060a0 face="Arial"> </font>
<td><font size=1 color=#0060a0 face="Arial"> Germany</font>
<tr>
<td colspan=4>
<hr>
<tr>
<td colspan=4><font size=1 color=#a2a2a2 face="Arial">IBM Deutschland Research
& Development GmbH / Vorsitzender des Aufsichtsrats: Martin Jetter
<br>
Geschaeftsfuehrung: Erich Baier <br>
Sitz der Gesellschaft: Boeblingen / Registergericht: Amtsgericht Stuttgart,
HRB 243294</font>
<tr>
<td colspan=4><font size=1 face="Arial"> </font>
<tr>
<td><font size=3> </font>
<td><font size=3> </font>
<td><font size=3> </font>
<td><font size=3> </font></table>
<br>