Subject: [patch 08/16] axon driver providing basic notifications Description: This patch provides files used for mailbox communication using the axon mailbox facility. Signed-off-by: Jesse Arroyo (arroyoj@us.ibm.com) Signed-off-by: H Brett Bolen (hbbolen@us.ibm.com) Signed-off-by: Murali Iyer (mniyer@us.ibm.com) Signed-off-by: Tim Schimke (tschimke@us.ibm.com) Index: linux-2.6.23.1/drivers/misc/triblade/axon_mailbox.c =================================================================== --- /dev/null +++ linux-2.6.23.1/drivers/misc/triblade/axon_mailbox.c @@ -0,0 +1,618 @@ +/** + * axon_mailbox - kernel suport for internal mailbox communication. + * + * The mailbox is a mechanism that allows the Axon-attached Cell processor + * to receive status messages concerning various processes and data + * transactions in its IO and environment. The processes send mailbox buffers + * of up to 128 bits (16 Bytes) that Axon places in a FIFO structure + * residing in the XDR memory (attached to the Cell). Communication between + * the Axon and the Cell is carried out through a standard write transaction + * through the BE interface. A mailbox buffer can be sent either by external + * devices (e.g., devices attached to the PCI-E) or internal devices + * (e.g., command completion by the DMA). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Copyright (C) IBM Corporation, 2008 + * + * Authors: H Brett Bolen , + * Tim Schimke , + * Jesse Arroyo , + * Murali N Iyer + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "axon_mailbox.h" +#include "axon.h" +#include "axon_hw.h" +#include "axon_task.h" + +#define MBX_MODULE_NAME "axon mailbox" +#define MAX_AXON_NUM 2 + +char *mbx_signature = MBX_MODULE_NAME; +char *mbx_driver_signature = "axon_mbx_driver"; +static int num_mbx_found; + +static inline u32 get_mailbox_dcr(struct mbx_dev *mbx_p, int reg) +{ + return dcr_read(mbx_p->mailbox_dcr_host, + mbx_p->mailbox_dcr_base + reg); +} + +static inline void set_mailbox_dcr(struct mbx_dev *mbx_p, int reg, u32 val) +{ + dcr_write(mbx_p->mailbox_dcr_host, + mbx_p->mailbox_dcr_base + reg, + val); +} + +static inline u32 get_c3po_dcr(struct mbx_dev *mbx_p, int reg) +{ + return dcr_read(mbx_p->c3po_dcr_host, mbx_p->c3po_dcr_base + reg); +} + +static inline void set_c3po_dcr(struct mbx_dev *mbx_p, int reg, u32 val) +{ + dcr_write(mbx_p->c3po_dcr_host, mbx_p->c3po_dcr_base + reg, val); +} + +static int mbx_fifo_size(struct mbx_dev *mbx_p) +{ + u32 reg = get_mailbox_dcr(mbx_p, MAILBOX_CONTROL); + int size; + + size = (reg>>8) & 0x03; + size = 0x8000 << size; + pr_debug("current fifo size = %dK\n", size/1024); + return size; +} + +static u32 mbx_calc_write(struct mbx_dev *mbx_p) +{ + int write = get_mailbox_dcr(mbx_p, MAILBOX_WRITE_OFFSET); + return (write % mbx_p->fifo_size); +} + +static int mbx_next_read(struct mbx_dev *mbx_p, u32 read_offset) +{ + u32 new_read = read_offset + MESSAGE_SIZE; + + if (new_read >= mbx_p->fifo_size) + new_read = 0; + + return new_read; +} + +static size_t mbx_drain_fifo(struct mbx_dev *mbx_p) +{ + int rc = 0; + int fifo_count = 0; + u32 read_offset; + u32 write_offset; + u32 last_read = get_mailbox_dcr(mbx_p, MAILBOX_READ_OFFSET); + u32 msg; + + read_offset = mbx_next_read(mbx_p, last_read); + write_offset = mbx_calc_write(mbx_p); + + pr_debug("read 0x%x, write 0x%x, mbx_buf %p\n", + read_offset, write_offset, mbx_p->mbx_buf); + + if (write_offset >= read_offset) + fifo_count = write_offset - read_offset; + else + fifo_count = (write_offset + mbx_p->fifo_size) - read_offset; + + pr_debug("Copy %u bytes from FIFO 0x%p\n", + fifo_count, mbx_p->mbx_buf+read_offset); + + while (fifo_count > 0) { + /* only first 4 bytes of the message are used */ + msg = *((u32 *)(mbx_p->mbx_buf+read_offset)); + pr_debug("Data = 0x%08x\n", msg); + axon_add_task( TQ_IRQ, + mbx_p->axon_priv, 0x0, msg, "NOTF"); + last_read = read_offset; + read_offset = mbx_next_read(mbx_p, read_offset); + fifo_count -= MESSAGE_SIZE; + rc++; + } + + set_mailbox_dcr(mbx_p, MAILBOX_READ_OFFSET, last_read); + pr_debug("return read 0x%x write 0x%x\n", + get_mailbox_dcr(mbx_p, MAILBOX_READ_OFFSET), + get_mailbox_dcr(mbx_p, MAILBOX_WRITE_OFFSET)); + + return rc; +} + +/* + * mbx_intr - Handle interrupts + * @irq: + * @dev_instance: + * @regs: + * The mailbox is using two interrupt lines connected to the MPIC. + * - Indirect mailbox interrupt - the mailbox generates an interrupt + * to indicate that a new message was written + * to the mailbox FIFO. During normal operation a direct interrupt + * is used (an interrupt that goes from the + * mailbox directly to the interrupt logic in the C3PO). + * This interrupt should not be in use in normal operation. + * - Mailbox FIFO Full interrupt - This interrupt indicates an + * FIFO full condition (i.e., the mailbox FIFO next + * write pointer is equal to the mailbox FIFO Read pointer). + * The interrupt is reported through the Axon interrupt + * controller (MPIC). + */ +static irqreturn_t mbx_intr(int irq, void *dev_instance) +{ + int rc = 0; + struct mbx_dev *mbx_p = dev_instance; + + pr_debug("Got IRQ %d, mbx_p %p\n", irq, mbx_p); + + if (!mbx_p->axon_priv) { + pr_debug("mbx interrupt occurred and axon_priv " + "not initialized"); + return IRQ_NONE; + } + + if (irq == mbx_p->irq_overflow) { + printk(KERN_ERR "mbx_intr: Overflow! FIFO operation " + "stopped by HW\n"); + /* CODETHIS what to do about this case? */ + } else if (irq == mbx_p->irq_indirect) { + /* drain the mailbox and put messages on work Q */ + rc = mbx_drain_fifo(mbx_p); + if (!rc) return IRQ_NONE; + + mbx_p->stats.indirect_ints += rc; + } else { + pr_debug("spurious or unexpected interrupt %d\n", irq); + return IRQ_NONE; + } + + return IRQ_HANDLED; +} + + +/** + * mbx_disable_irqs - + + * @mbx_p: + * + * Description: Disable IRQ's + */ +static void mbx_disable_irqs(struct mbx_dev *mbx_p) +{ +/* FIXME add Direct interrupt if/when supported */ + disable_irq(mbx_p->irq_indirect); + disable_irq(mbx_p->irq_overflow); +} + +/** + * mbx_setup_irqs + * + */ +static int mbx_setup_irqs(struct mbx_dev *mbx_p) +{ + int rc = 0; + + /* FIXME add Direct interrupt if/when supported */ + rc = request_irq(mbx_p->irq_indirect, + mbx_intr, + 0, + "axon_mailbox indirect", + mbx_p); + if (rc) { + printk(KERN_ERR "mbx_setup_irqs: request_irq() failed" + "errno = %d, irq = 0x%x\n", + rc, + mbx_p->irq_indirect); + return rc; + } + pr_debug("IRQ[0]= %d\n", mbx_p->irq_indirect); + + rc = request_irq(mbx_p->irq_overflow, + mbx_intr, + 0, + "axon_mailbox overflow", + mbx_p); + if (rc) { + printk(KERN_ERR "mbx_setup_irqs: request_irq() failed" + "errno = %d, irq = 0x%x\n", + rc, + mbx_p->irq_overflow); + + free_irq(mbx_p->irq_indirect, (void *)0); + } + pr_debug("IRQ[1]= %d\n", mbx_p->irq_overflow); + + return rc; +} + +/** + * mbx_enable - + * @flag: 1 - enable, 0 - disable + * + */ +static void mbx_enable(struct mbx_dev *mbx_p, int flag) +{ + + u32 reg = get_mailbox_dcr(mbx_p, MAILBOX_CONTROL); + u32 c3po_mask_reg = + get_c3po_dcr(mbx_p, C3PO_MAILBOX_REGION_MASK_LO); + + if (flag) { + reg |= MAILBOX_ENABLE; + pr_debug("Mailbox enabled control = 0x%x\n", reg); + /* + * Set VAL bit in 18.5.13 Mailbox Access Region Mask Low Reg + */ + c3po_mask_reg |= MAILBOX_REGION_MASK_LO_VAL; + } else { + reg &= ~MAILBOX_ENABLE; + pr_debug("Mailbox disabled control = 0x%x\n", reg); + /* + * Clear VAL bit in 18.5.13 Mailbox Access Region Mask Low Reg + */ + c3po_mask_reg &= ~MAILBOX_REGION_MASK_LO_VAL; + } + set_mailbox_dcr(mbx_p, MAILBOX_CONTROL, reg); + set_c3po_dcr(mbx_p, C3PO_MAILBOX_REGION_MASK_LO, c3po_mask_reg); +} + +/* + Find node c3po dcr base +*/ + +static long +c3po_find_base(struct device_node *dn, struct mbx_dev *mbx_p) +{ + /* incoming device_node points at mailbox node */ + + /* get c3po dcr properties to enable / disable mailbox interface */ + mbx_p->c3po_dcr_base = dcr_resource_start(dn, 1); + mbx_p->c3po_dcr_len = dcr_resource_len(dn, 1); + + mbx_p->c3po_dcr_host = dcr_map(dn, + mbx_p->c3po_dcr_base, + mbx_p->c3po_dcr_len); + + if (!DCR_MAP_OK(mbx_p->c3po_dcr_host)) { + printk(KERN_ERR "failed to map c3po DCRs !\n"); + mbx_p->c3po_dcr_base = 0; + return -1; + } + pr_debug("c3po dcr_base 0x%x, len = %d, mapped to %p\n", + mbx_p->c3po_dcr_base, + mbx_p->c3po_dcr_len, + mbx_p->c3po_dcr_host.token); + return 0; +} + +/** + * mbx_find_base - + * + */ +static int mbx_find_base(struct device_node *dn, struct mbx_dev *mbx_p) +{ + + mbx_p->mbxreg_base_addr = (void __iomem *) of_iomap(dn, 0); + + if (!mbx_p->mbxreg_base_addr) { + pr_debug("ioremap failed for mailbox regs\n"); + return -ENODEV; + } + + pr_debug("mmio mailbox mapped at %p\n", mbx_p->mbxreg_base_addr); + + mbx_p->mailbox_dcr_base = dcr_resource_start(dn, 0); + mbx_p->mailbox_dcr_len = dcr_resource_len(dn, 0); + if (mbx_p->mailbox_dcr_base == 0 || !mbx_p->mailbox_dcr_len) { + printk(KERN_ERR "can't find DCR resource! or " + "length is zero!\n"); + mbx_p->mailbox_dcr_base = 0; + return -ENODEV; + } + + mbx_p->mailbox_dcr_host = dcr_map(dn, mbx_p->mailbox_dcr_base, + mbx_p->mailbox_dcr_len); + if (!DCR_MAP_OK(mbx_p->mailbox_dcr_host)) { + printk(KERN_ERR "mailbox: failed to map DCRs !\n"); + mbx_p->mailbox_dcr_base = 0; + return -ENODEV; + } + pr_debug("mbx dcr_base 0x%x, len = 0x%x, mapped to 0x%p\n", + mbx_p->mailbox_dcr_base, mbx_p->mailbox_dcr_len, + mbx_p->mailbox_dcr_host.token); + + mbx_p->irq_indirect = irq_of_parse_and_map(dn, 0); + mbx_p->irq_overflow = irq_of_parse_and_map(dn, 1); + + pr_debug("DCR base = 0x%x\n", mbx_p->mailbox_dcr_base); + return 0; +} + +/** + * mbx_hw_setup - + * + * During chip initialization, the following operations must be + * carried out to prepare the mailbox for operation: + * - Configure the mailbox buffer target address in the + * MailboxMessageAddress Register + * - Configure the XDR location of the mailbox FIFO in the + * MailboxBaseAddresss Register + * - Configure the mailbox size and the interrupt mask and + * set the enable bit in the MailboxControl Register + * There is no need to initialize the read and write pointers. + * + */ +static int mbx_hw_setup(struct of_device *ofdev, struct mbx_dev *mbx_p) +{ + /* Get Mailbox buffer memory assigned */ + mbx_p->mbx_buf = dma_alloc_coherent(&ofdev->dev, MAX_MBX_FIFO, + &mbx_p->buf_da, GFP_KERNEL); + if (!mbx_p->mbx_buf) { + printk(KERN_ERR "Unable to get dma pages\n"); + return -ENOMEM; + } + + /* mailbox needs to be 64KB aligned */ + if ((u64)mbx_p->mbx_buf & 0xffff) { + printk(KERN_ERR "Mailbox buffer not 64KB aligned.\n"); + return -ENOMEM; + } + pr_debug("mailbox buffer= %p, buf_da= 0x%lx\n", + mbx_p->mbx_buf, mbx_p->buf_da); + + /* Write default mailbox location as per AXON specs. */ + set_mailbox_dcr(mbx_p, MAILBOX_MESSAGE_HI, PLB5_DEV_BASE_HI); + set_mailbox_dcr(mbx_p, MAILBOX_MESSAGE_LO, DEV_MBX_MSG0_OFFSET); + + /* Set write buffer location */ + set_mailbox_dcr(mbx_p, MAILBOX_BASE_HI, + ((u64)mbx_p->buf_da>>32) & 0xffffffff); + set_mailbox_dcr(mbx_p, MAILBOX_BASE_LO, + (u64)mbx_p->buf_da & 0xfffffff0); + + pr_debug("mailbox regs: MAILBOX_MESSAGE= 0x%08x_%08x,\n", + get_mailbox_dcr(mbx_p, MAILBOX_MESSAGE_HI), + get_mailbox_dcr(mbx_p, MAILBOX_MESSAGE_LO)); + pr_debug("MAILBOX_BASE= 0x%08x_%08x\n", + get_mailbox_dcr(mbx_p, MAILBOX_BASE_HI), + get_mailbox_dcr(mbx_p, MAILBOX_BASE_LO)); + + /* Initialize read and write pointers */ + set_mailbox_dcr(mbx_p, MAILBOX_READ_OFFSET, MAILBOX_OFFSET); + set_mailbox_dcr(mbx_p, MAILBOX_WRITE_OFFSET, 0); + + /* + * Interrupt on full + * Indirect interrupts via MPIC + * Stop on full + * 64K mailbox + */ + set_mailbox_dcr(mbx_p, MAILBOX_CONTROL, + MAILBOX_STOP_FULL | MAILBOX_FULL_INTR | + MAILBOX_INDIRECT_INTR | MAILBOX_SIZE_64K); + mbx_p->fifo_size = mbx_fifo_size(mbx_p); + pr_debug("MAILBOX_CONTROL= 0x%08x\n", + get_mailbox_dcr(mbx_p, MAILBOX_CONTROL)); + + return 0; +} + + +/** + * mbx_cleanup + * release all resources that have been acquired + */ +static void mbx_cleanup(struct of_device *ofdev, struct mbx_dev *mbx_p) +{ + if (mbx_p->c3po_dcr_base != 0) { + dcr_unmap(mbx_p->c3po_dcr_host, + mbx_p->c3po_dcr_base, + mbx_p->c3po_dcr_len); + mbx_p->c3po_dcr_base = 0; + } + if (mbx_p->mailbox_dcr_base != 0) { + dcr_unmap(mbx_p->mailbox_dcr_host, + mbx_p->mailbox_dcr_base, + mbx_p->mailbox_dcr_len); + mbx_p->mailbox_dcr_base = 0; + } + + if (mbx_p->mbxreg_base_addr != 0) { + iounmap((void __iomem *)mbx_p->mbxreg_base_addr); + mbx_p->mbxreg_base_addr = 0; + } + if (mbx_p->mbx_buf != NULL) { + dma_free_coherent(&ofdev->dev, + MAX_MBX_FIFO, + mbx_p->mbx_buf, + mbx_p->buf_da); + mbx_p->mbx_buf = NULL; + } +} + +/** + * mbx_probe - probe() method for platform driver + * @device, @device_id: see of_platform_driver method + */ +static int +mbx_probe(struct of_device *ofdev, const struct of_device_id *device_id) +{ + int rc = 0; + struct mbx_dev *mbx_p; + int index = num_mbx_found++; + + pr_debug("Found %s%d on %s\n", MBX_MODULE_NAME, index, + ofdev->node->full_name); + + + mbx_p = kzalloc( sizeof(struct mbx_dev), GFP_KERNEL); + if (!mbx_p) { + printk(KERN_ERR "mbx%d: out of memory allocating mbx " + "structure.\n", + index); + return -ENOMEM; + } + + mbx_p->signature = mbx_signature; + mbx_p->index = index; + sprintf((char *)&mbx_p->name[0], "%s%d", mbx_signature, mbx_p->index); + + rc = mbx_find_base(ofdev->node, mbx_p); + if (rc) { + printk(KERN_ERR "Mailbox: can't get the registers\n"); + goto error; + } + + rc = c3po_find_base(ofdev->node, mbx_p); + if (rc) { + printk(KERN_ERR "Can't find c3po node or properties\n"); + goto error; + } + + rc = mbx_hw_setup(ofdev, mbx_p); + if (rc) { + printk(KERN_ERR "Mailbox hardware initialization failed.\n"); + goto error; + } + + rc = mbx_setup_irqs(mbx_p); + if (rc) { + printk(KERN_ERR "mbx: mbx_setup_irqs() failed " + "errno = %d\n", rc); + goto error; + } + + dev_set_drvdata(&ofdev->dev, (void *)mbx_p); + + /* enable the mailbox to receive messages */ + mbx_enable(mbx_p, 1); + + pr_debug("Probe of %s%d on %s complete.\n", MBX_MODULE_NAME, + mbx_p->index, ofdev->node->full_name); + return 0; + +error: + mbx_cleanup(ofdev, mbx_p); + return rc; +} + +/** + * mbx_remove - remove() method for platform driver + * @device: see of_platform_driver method + */ +static int +mbx_remove(struct of_device *ofdev) +{ + struct mbx_dev *mbx_p = (struct mbx_dev *) + dev_get_drvdata(&ofdev->dev); + pr_debug("mbx_dev/mbx%d pointer at %p, mmio_addr = %p\n", + mbx_p->index, mbx_p, mbx_p->mbxreg_base_addr); + + /* Disable hardware */ + mbx_enable(mbx_p, 0); + + /* + * Disable interrupts + */ + mbx_disable_irqs(mbx_p); + + /* Free IRQ's */ + /* free_irq(140, (void *)0); FIXME direct int */ + free_irq(mbx_p->irq_indirect, mbx_p); + free_irq(mbx_p->irq_overflow, mbx_p); + + /* release resources */ + mbx_cleanup(ofdev, mbx_p); + + dev_set_drvdata(&ofdev->dev, NULL); + + pr_debug("Uninstalled (remove) %s%d on %s complete.\n", + MBX_MODULE_NAME, + mbx_p->index, ofdev->node->full_name); + kfree(mbx_p); + + return 0; +} + +/* + * NOTE: We do not have a "compatible" entry in the device tree yet. + * Once that is added, it needs to be updated here. + * This should be along the lines of "ibm,mailbox-axon" + */ +static struct of_device_id mbx_device_id[] = { + { + .type = "mailbox" + }, + {} +}; + +static struct of_platform_driver axon_mbx_driver = { + .owner = THIS_MODULE, + .name = MBX_MODULE_NAME, + .match_table = mbx_device_id, + .probe = mbx_probe, + .remove = mbx_remove, +}; + +/** + * mbx_init + */ +int __init mbx_init(void) +{ + num_mbx_found = 0; + return of_register_platform_driver(&axon_mbx_driver); +} + +/** + * mbx_exit + */ +void __exit mbx_exit(void) +{ + of_unregister_platform_driver(&axon_mbx_driver); +} Index: linux-2.6.23.1/drivers/misc/triblade/axon_mailbox.h =================================================================== --- /dev/null +++ linux-2.6.23.1/drivers/misc/triblade/axon_mailbox.h @@ -0,0 +1,133 @@ +/** + * axon_mailbox - kernel suport for internal mailbox communication. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Copyright (C) IBM Corporation, 2008 + * + * Authors: H Brett Bolen , + * Tim Schimke , + * Jesse Arroyo , + * Murali N Iyer + * + */ + + +#ifndef __AXON_MBX_H +#define __AXON_MBX_H + +#include +#include +#include +#include + +/* function prototypes */ +int mbx_init(void); /* mailbox driver initialization */ +void mbx_exit(void); /* mailbox driver exit */ + + +#define MAX_MBX_FIFO 64*1024 + +#define MBX_DEVICE_NAME_LEN 25 /* size of the device name */ + +struct mbx_stats{ + uint32_t indirect_ints; + uint32_t direct_ints; + uint32_t indirect_latency; + uint32_t direct_latency; +}; + +/* + * Device Structure + */ +struct mbx_dev{ + char *signature; /* Structure signature */ + int index; /* Index number of device */ + char name[MBX_DEVICE_NAME_LEN]; /* Name of the device */ + + char *mbx_buf; /* mailbox message buffer */ + dma_addr_t buf_da; /* DMA address of the mailbox */ + u32 fifo_size; /* size of message buffer */ + + void __iomem *mbxreg_base_addr; /* mmio addr of mailbox regs */ + + dcr_host_t mailbox_dcr_host; /* mapped mailbox dcr address */ + int mailbox_dcr_base; /* phys addr of mailbox dcr base */ + int mailbox_dcr_len; /* mailbox dcr length */ + + dcr_host_t c3po_dcr_host; /* mapped c3po dcr address */ + int c3po_dcr_base; /* phys addr of c3po dcr base */ + int c3po_dcr_len; /* c3po dcr length */ + + u8 irq_indirect; /* IRQ mapping info */ + u8 irq_overflow; + + struct mbx_stats stats; + + void *axon_priv; /* needed by IRQ handler */ +}; + + +#define MESSAGE_SIZE 16 + +#define MAILBOX_CONTROL 0 +#define MAILBOX_SIZE_32K 0x00000000 +#define MAILBOX_SIZE_64K 0x00000100 +#define MAILBOX_SIZE_128K 0x00000200 +#define MAILBOX_SIZE_256K 0x00000300 +#define MAILBOX_STOP_FULL 0x00000010 +#define MAILBOX_INDIRECT_INTR 0x00000008 +#define MAILBOX_DIRECT_INTR 0x00000004 +#define MAILBOX_FULL_INTR 0x00000002 +#define MAILBOX_ENABLE 0x00000001 + +#define MAILBOX_MESSAGE_HI 1 /* This value is compared with + * bits 0 to 31 of the incoming + * transaction to check if it is + * a valid Mailbox message. + */ +#define MAILBOX_MESSAGE_LO 2 /* This value is compared with + * bits 32 to 59 of the incoming + * transaction to check if it is + * a valid Mailbox message. + */ +#define MAILBOX_BASE_HI 3 /* Bit 0:31 of the mailbox FIFO base + * address (on the GBIF address bus). + */ +#define MAILBOX_BASE_LO 4 /* Bit 32:45 of the mailbox FIFO base + * address (on the GBIF address bus). + */ +#define MAILBOX_READ_OFFSET 5 +#define MAILBOX_OFFSET 0x0003fff0 /* This pointer is an offset to the + * Mailbox pointing to the next Mailbox + * FIFO entry that will be read by the + * software. This register is used only + * to indicate Mailbox FIFO overflow + * condition. To allow FIFO overrun + * error indication, the + * MAILBOX_FULL_INTR bit in the + * MAILBOX_CONTROL register must be set + */ +#define MAILBOX_WRITE_OFFSET 6 + +/* + C3PO DCR register definition related to Mailbox function. + Base DCR address is second dcr-reg parameter in device-tree (0x51) +*/ +#define C3PO_MAILBOX_REGION_MASK_LO 0x0 +#define MAILBOX_REGION_MASK_LO_VAL 0x00000001 /* Bit 0 indicates */ + /* region is valid */ +#endif /* __AXON_MBX_H */ + --