diff -paurNX diff_file_exclusion oprofile/configure.in oprofile-with-cell/configure.in --- oprofile/configure.in 2006-09-15 17:40:08.000000000 -0500 +++ oprofile-with-cell/configure.in 2006-11-15 11:32:15.547231904 -0600 @@ -20,6 +20,7 @@ AC_PROG_RANLIB dnl for the man page DATE="`date '+%a %d %B %Y'`" AC_SUBST(DATE) +AC_SUBST(DESTDIR) dnl needed for module build OPROFILE_DIR=`pwd` diff -paurNX diff_file_exclusion oprofile/doc/oprofile.xml oprofile-with-cell/doc/oprofile.xml --- oprofile/doc/oprofile.xml 2006-11-15 10:33:26.000000000 -0600 +++ oprofile-with-cell/doc/oprofile.xml 2006-11-15 11:32:19.277197248 -0600 @@ -93,6 +93,10 @@ OProfile is not a panacea. OProfile migh PPC64 processors (Power4/Power5/PPC970) require a recent (> 2.6.5) kernel with the line #define PV_970 present in include/asm-ppc64/processor.h. ++ ++ ++ PPC64 processors (Cell) require a recent (> 2.6.18) kernel with the line ++ #define PV_BE present in include/asm-powerpc/reg.h. @@ -804,7 +808,7 @@ The table below lists the events selecte Itanium 2ia64/itanium2CPU_CYCLES:100000:0:1:1 TIMER_INTtimerNone selectable IBM iseriesPowerPC 4/5/970CYCLES:10000:0:1:1 -IBM pseriesPowerPC 4/5/970CYCLES:10000:0:1:1 +IBM pseriesPowerPC 4/5/970/CellCYCLES:10000:0:1:1 IBM s390timerNone selectable IBM s390xtimerNone selectable diff -paurNX diff_file_exclusion oprofile/events/Makefile.am oprofile-with-cell/events/Makefile.am --- oprofile/events/Makefile.am 2006-08-22 16:24:32.000000000 -0500 +++ oprofile-with-cell/events/Makefile.am 2006-11-15 11:32:19.279196944 -0600 @@ -20,6 +20,7 @@ event_files = \ ppc64/power5/events ppc64/power5/event_mappings ppc64/power5/unit_masks \ ppc64/power5+/events ppc64/power5+/event_mappings ppc64/power5+/unit_masks \ ppc64/970/events ppc64/970/event_mappings ppc64/970/unit_masks \ + ppc64/cell-be/events ppc64/cell-be/unit_masks \ rtc/events rtc/unit_masks \ x86-64/hammer/events x86-64/hammer/unit_masks \ arm/xscale1/events arm/xscale1/unit_masks \ diff -paurNX diff_file_exclusion oprofile/events/ppc64/cell-be/events oprofile-with-cell/events/ppc64/cell-be/events --- oprofile/events/ppc64/cell-be/events 1969-12-31 18:00:00.000000000 -0600 +++ oprofile-with-cell/events/ppc64/cell-be/events 2006-11-15 11:48:03.625281000 -0600 @@ -0,0 +1,531 @@ +# ppc64 Cell Broadband Engine events +# +# As many as 8 signals may be specified when they are from the same group. +# In some instances, signals from other groups in the same island or one +# other island may also be specified. +# +# Each signal is assigned to a unique counter. There are 4 32-bit hardware +# counters, each of which may be subdivided into 2 16-bit counters. The +# signals are defined in the Cell Broadband Engine Performance manual. +# +# Each event is given a unique event number. The event number is used by the +# Oprofile code to resolve event names for the postprocessing. This is done +# to preserve compatibility with the rest of the Oprofile code. The event +# number format group_num followed by the counter number for the event within +# the group. + +# Signal Default +event:0x1 counters:0,1,2,3 um:zero minimum:1000 name:CYCLES : Processor Cycles + + +# Cell BE Island 2 - PowerPC Processing Unit (PPU) + +# CBE Signal Group 21 - PPU Instruction Unit - Group 1 (NClk) +event:0x834 counters:0,1,2,3 um:PPU_01_edges minimum:10000 name:Branch_Commit : Branch instruction committed. +event:0x835 counters:0,1,2,3 um:PPU_01_edges minimum:10000 name:Branch_Flush : Branch instruction that caused a misprediction flush is committed. Branch misprediction includes: (1) misprediction of taken or not-taken on conditional branch, (2) misprediction of branch target address on bclr[1] and bcctr[1]. +event:0x836 counters:0,1,2,3 um:PPU_01_cycles minimum:10000 name:Ibuf_Empty : Instruction buffer empty. +event:0x837 counters:0,1,2,3 um:PPU_01_edges minimum:10000 name:IERAT_Miss : Instruction effective-address-to-real-address translation (I-ERAT) miss. +event:0x838 counters:0,1,2,3 um:PPU_01_cycles_or_edges minimum:10000 name:IL1_Miss_Cycles : L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions (see Note 1). +event:0x83a counters:0,1,2,3 um:PPU_01_cycles minimum:10000 name:Dispatch_Blocked : Valid instruction available for dispatch, but dispatch is blocked. +event:0x83d counters:0,1,2,3 um:PPU_01_edges minimum:10000 name:Instr_Flushed : Instruction in pipeline stage EX7 causes a flush. +event:0x83f counters:0,1,2,3 um:PPU_01_edges minimum:10000 name:PPC_Commit : Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle. + + +# CBE Signal Group 22 - PPU Execution Unit (NClk) +event:0x89a counters:0,1,2,3 um:PPU_01_cycles minimum:10000 name:DERAT_Miss : Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative. +event:0x89b counters:0,1,2,3 um:PPU_01_cycles minimum:10000 name:Store_Request : Store request counted at the L2 interface. Counts microcoded PPE sequences more than once (see Note 1 for exceptions). (Thread 0 and 1) +event:0x89c counters:0,1,2,3 um:PPU_01_cycles minimum:10000 name:Load_Valid : Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions. +event:0x89d counters:0,1,2,3 um:PPU_01_cycles minimum:10000 name:DL1_Miss : L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well. + + +# Cell BE Island 3 - PowerPC Storage Subsystem (PPSS) + +# CBE Signal Group 31 - PPSS Bus Interface Unit (NClk/2) +event:0xc1c counters:0,1,2,3 um:PPU_2_edges minimum:10000 name:rcv_mmio_rd_ev : Load from MFC memory-mapped I/O (MMIO) space. +event:0xc1d counters:0,1,2,3 um:PPU_2_edges minimum:10000 name:rcv_mmio_wr_ev : Stores to MFC MMIO space. +event:0xc22 counters:0,1,2,3 um:PPU_2_edges minimum:10000 name:even_token_req_ev : Request token for even memory bank numbers 0-14. +event:0xc2b counters:0,1,2,3 um:PPU_2_edges minimum:10000 name:rcv_data_ev : Receive 8-beat data from the Element Interconnect Bus (EIB). +event:0xc2c counters:0,1,2,3 um:PPU_2_edges minimum:10000 name:send_data_ev : Send 8-beat data to the EIB. +event:0xc2d counters:0,1,2,3 um:PPU_2_edges minimum:10000 name:send_cmd_ev : Send a command to the EIB; includes retried commands. +event:0xc2e counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:dgnt_dly_cy : Cycles between data request and data grant. +event:0xc33 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:nc_wr_not_emp_cy : The five-entry Non-Cacheable Unit (NCU) Store Command queue not empty. + + +# CBE Signal Group 32 - PPSS L2 Cache Controller - Group 1 (NClk/2) +event:0xc80 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:cache_hit : Cache hit for core interface unit (CIU) loads and stores. +event:0xc81 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:cache_miss : Cache miss for CIU loads and stores. +event:0xc84 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:load_miss : CIU load miss. +event:0xc85 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:store_miss : CIU store to Invalid state (miss). +event:0xc87 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:larx_miss_th1 : Load word and reserve indexed (lwarx/ldarx) for Thread 0 hits Invalid cache state +event:0xc8e counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:stcx_miss_th1 : Store word conditional indexed (stwcx/stdcx) for Thread 0 hits Invalid cache state when reservation is set. +event:0xc99 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:all_snp_busy : All four snoop state machines busy. + +# CBE Signal Group 33 - PPSS L2 Cache Controller - Group 2 (NClk/2) +event:0xce8 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:dclaim_srt : Data line claim (dclaim) that received good combined response; includes store/stcx/dcbz to Shared (S), Shared Last (SL),or Tagged (T) cache state; does not include dcbz to Invalid (I) cache state (see Note 1). +event:0xcef counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:dclaim_to_rwitm : Dclaim converted into rwitm; may still not get to the bus if stcx is aborted (see Note 2). +event:0xcf0 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:store_mxe : Store to modified (M), modified unsolicited (MU), or exclusive (E) cache state. +event:0xcf1 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:stq_full : 8-entry store queue (STQ) full. +event:0xcf2 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:store_rc_ack : Store dispatched to RC machine is acknowledged. +event:0xcf3 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:gather_store : Gatherable store (type = 00000) received from CIU. +event:0xcf6 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_push : Snoop push. +event:0xcf7 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:intv_snode_er : Send intervention from (SL | E) cache state to a destination within the same CBE chip. +event:0xcf8 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:intv_snode_mx : Send intervention from (M | MU) cache state to a destination within the same CBE chip. +event:0xcfd counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_retry : Respond with Retry to a snooped request due to one of the following conflicts: read-and-claim state machine (RC) full address, castout (CO) congruence class, snoop (SNP) machine full address, all snoop machines busy, directory lockout, or parity error. +event:0xcfe counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_busy_retry : Respond with Retry to a snooped request because all snoop machines are busy. +event:0xcff counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_mx_to_est : Snooped response causes a cache state transition from (M | MU) to (E | S | T). +event:0xd00 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_e_to_s : Snooped response causes a cache state transition from E to S. +event:0xd01 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_esrt_to_i : Snooped response causes a cache state transition from (E | SL | S | T) to Invalid (I). +event:0xd02 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_mx_to_i : Snooped response causes a cache state transition from (M | MU) to I. + +# CBE Signal Group 34 - PPSS L2 Cache Controller - Group 3 (NClk/2) +event:0xd54 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:larx_miss : Load and reserve indexed (lwarx/ldarx) for Thread 1 hits Invalid cache state. +event:0xd5b counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:stcx_miss_th2 : Store conditional indexed (stwcx/stdcx) for Thread 1 hits Invalid cache state. + +# CBE Signal Group 35 - PPSS Non-Cacheable Unit (NClk/2) +event:0xdac counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:st_req_any : Non-cacheable store request received from CIU; includes all synchronization operations such as sync and eieio. +event:0xdad counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:st_req_sync : sync received from CIU. +event:0xdb0 counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:st_req_store : Non-cacheable store request received from CIU; includes only stores. +event:0xdb2 counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:st_req_eieio : eieio received from CIU. +event:0xdb3 counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:st_req_tlbie : tlbie received from CIU. +event:0xdb4 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stq_bot_sync : sync at the bottom of the store queue, while waiting on st_done signal from the Bus Interface Unit (BIU) and sync_done signal from L2. +event:0xdb5 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stq_bot_lsync : lwsync at the bottom of the store queue, while waiting for a sync_done signal from the L2. +event:0xdb6 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stq_bot_eieio : eieio at the bottom of the store queue, while waiting for a st_done signal from the BIU and a sync_done signal from the L2. +event:0xdb7 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stq_bot_tlbieg : tlbie at the bottom of the store queue, while waiting for a st_done signal from the BIU. +event:0xdb8 counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:st_combined : Non-cacheable store combined with the previous non-cacheable store with a contiguous address. +event:0xdb9 counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:ld_cancel : Load request canceled by CIU due to late detection of load-hit-store condition (128B boundary). +event:0xdba counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:ld_hit_st : NCU detects a load hitting a previous store to an overlapping address (32B boundary). +event:0xdbb counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stb_full : All four store-gather buffers full. +event:0xdbc counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:ld_req : Non-cacheable load request received from CIU; includes instruction and data fetches. +event:0xdbd counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stq_not_empty : The four-deep store queue not empty. +event:0xdbe counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stq_full : The four-deep store queue full. +event:0xdbf counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stb_not_empty : At least one store gather buffer not empty. + +# Cell BE Island 4 - Synergistic Processor Unit (SPU) + +# CBE Signal Group 41 - SPU (NClk) + +# CBE Signal Group 42 - SPU Trigger (NClk) + +# CBE Signal Group 43 - SPU Event (NClk) +event:0x110b counters:0,1,2,3 um:SPU_Event_edges minimum:10000 name:Address_trace : Serialized SPU Address (program counter) Trace + + + +# Cell BE Island 5 - Memory Flow Control (MFC) + +# CBE Signal Group 51 - MFC Atomic Unit (NClk/2) +event:0x13ed counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:ato_loads : Atomic load received from direct memory access controller (DMAC). +event:0x13ee counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:ato_dclaims : Atomic dclaim sent to synergistic bus interface (SBI); includes retried requests. +event:0x13ef counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:ato_rwitms : Atomic rwitm performed sent to SBI; includes retried requests. +event:0x13f0 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:ato_ld_mu : Atomic load miss caused MU cache state. +event:0x13f1 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:ato_ld_e : Atomic load miss caused E cache state. +event:0x13f2 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:ato_ld_r : Atomic load miss caused SL cache state. +event:0x13f3 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:ato_ld_hit : Atomic load hits cache. +event:0x13f4 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:ato_ld_mis_w_intv : Atomic load misses cache with data intervention; sum of signals 4 and 6 in this group. +event:0x13fa counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:puts_mis_wo_intv : putllc or putlluc misses cache without data intervention; for putllc, counts only when reservation is set for the address. +event:0x13fd counters:0,1,2,3 um:SPU_02_cycles minimum:10000 name:snfsm_busy : Snoop machine busy. +event:0x13ff counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:snp_mx_to_i : Snoop caused cache transition from [M | MU] to I. +event:0x1401 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:snp_ers_to_i : Snoop caused cache transition from [E | S | SL] to I. +event:0x1403 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:snp_mu_to_t : Snoop caused cache transition from MU to T cache state. +event:0x1407 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:snp_mx_intv_loc : Sent modified data intervention to a destination within the same CBE chip. + +# CBE Signal Group 52 - MFC Direct Memory Access Controller (NClk/2) +event:0x1450 counters:0,1,2,3 um:SPU_0_edges minimum:10000 name:All_DMA_get[]_cmd : Any flavor of DMA get[] command issued to Synergistic Bus Interface (SBI); sum of signals 17-25 in this group. +event:0x1451 counters:0,1,2,3 um:SPU_0_edges minimum:10000 name:All_DMA_put[]_cmd : Any flavor of DMA put[] command issued to SBI; sum of signals 2-16 in this group. +event:0x1452 counters:0,1,2,3 um:SPU_0_edges minimum:10000 name:DMA_put : DMA put (put) is issued to SBI. +event:0x1461 counters:0,1,2,3 um:SPU_0_edges minimum:10000 name:DMA_get : DMA get data from effective address to local storage (get) issued to SBI. + + +# CBE Signal Group 53 - MFC Synergistic Bus Interface (NClk/2) +event:0x14b7 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:evp_lcmd_rq_full : Sent retry to a local command due toeight8-deep snoop read queue being full (see Note 1). +event:0x14b8 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:evp_load_req : Load request sent to element interconnect bus (EIB); includes read, read atomic, rwitm, rwitm atomic, and retried commands. +event:0x14b9 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:evp_store_req : Store request sent to EIB; includes wwf, wwc, wwk, dclaim, dclaim atomic, and retried commands. +event:0x14ba counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:evp_receive_dat : Received data from EIB, including partial cache line data. +event:0x14bb counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:evp_send_dat : Sent data to EIB, both as a master and a snooper. +event:0x14bc counters:0,1,2,3 um:SPU_02_cycles minimum:10000 name:evp_queue_not_empty : 16-deep synergistic bus interface (SBI) queue with outgoing requests not empty; does not include atomic requests. +event:0x14bd counters:0,1,2,3 um:SPU_02_cycles minimum:10000 name:evp_queue_full : 16-deep SBI queue with outgoing requests full; does not include atomic requests. +event:0x14be counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:evp_cmdv : Sent request to EIB. +event:0x14c0 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:evp_dgrant : Received data bus grant; includes data sent for MMIO operations. +event:0x14c1 counters:0,1,2,3 um:SPU_02_cycles minimum:10000 name:evp_wait_dgrant : Cycles between data bus request and data bus grant. +event:0x14c2 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:evp_token_mc_odd : Command (read or write) for an odd-numbered memory bank; valid only when resource allocation is turned on. +event:0x14c3 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:evp_token_mc_even : Command (read or write) for an even-numbered memory bank; valid only when resource allocation is turned on. +event:0x14c6 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:evp_mst_retry : Request gets the Retry response; includes local and global requests. +event:0x14c7 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:evp_dreq : Sent data bus request to EIB. + + +# CBE Signal Group 54 - MFC Synergistic Memory Management (NClk/2) +event:0x1518 counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:tlb_miss_e : Translation Lookaside Buffer (TLB) miss without parity or protection errors. +event:0x1519 counters:0,1,2,3 um:SPU_02_cycles minimum:10000 name:tlb_miss_c : TLB miss (cycles). +event:0x151a counters:0,1,2,3 um:SPU_02_edges minimum:10000 name:tlb_hit : TLB hit. + + +# Cell BE Island 6 - Element Interconnect Bus (EIB) + +# CBE Signal Group 61 - EIB Address Concentrator 0 (NClk/2) +event:0x17d4 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_ICMD_PERF(0) : Number of read and rwitm commands (including atomic) AC1 to AC0. (Group 1) +event:0x17d5 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_ICMD_PERF(1) : Number of dclaim commands (including atomic) AC1 to AC0. (Group 1) +event:0x17d6 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_ICMD_PERF(2) : Number of wwk, wwc, and wwf commands from AC1 to AC0. (Group 1) +event:0x17d7 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_ICMD_PERF(3) : Number of sync, tlbsync, and eieio commands from AC1 to AC0. (Group 1) +event:0x17d8 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_ICMD_PERF(4) : Number of tlbie commands from AC1 to AC0. (Group 1) +event:0x17df counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_CAM_PERF(1) : Previous adjacent address match (PAAM) Content Addressable Memory (CAM) hit. (Group 1) +event:0x17e0 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_CAM_PERF(2) : PAAM CAM miss. (Group 1) +event:0x17e2 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_CAM_CMD_REFLECTED : Command reflected. (Group 1) +event:0x17e4 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_ICMD_PERF(0) : Number of read and rwitm commands (including atomic) AC1 to AC0. (Group 2) +event:0x17e5 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_ICMD_PERF(1) : Number of dclaim commands (including atomic) AC1 to AC0. (Group 2) +event:0x17e6 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_ICMD_PERF(2) : Number of wwk, wwc, and wwf commands from AC1 to AC0. (Group 2) +event:0x17e7 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_ICMD_PERF(3) : Number of sync, tlbsync, and eieio commands from AC1 to AC0. (Group 2) +event:0x17e8 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_ICMD_PERF(4) : Number of tlbie commands from AC1 to AC0. (Group 2) +event:0x17ef counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_CAM_PERF(1) : PAAM CAM hit. (Group 2) +event:0x17f0 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_CAM_PERF(2) : PAAM CAM miss. (Group 2) +event:0x17f2 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0.W_CAM_CMD_REFLECTED : Command reflected. (Group 2) + +# CBE Signal Group 62 - EIB Address Concentrator 1 (NClk/2) +event:0x1839 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(1) : Local command from SPE 6. +event:0x183a counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(2) : Local command from SPE 4. +event:0x183b counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(3) : Local command from SPE 2. +event:0x183c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(4) : Local command from SPE 0. +event:0x183d counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(5) : Local command from PPE. +event:0x183e counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(6) : Local command from SPE 1. +event:0x183f counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(7) : Local command from SPE 3. +event:0x1840 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(8) : Local command from SPE 5. +event:0x1841 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(9) : Local command from SPE 7. +event:0x1844 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(12) : AC1-to-AC0 global command from SPE 6. +event:0x1845 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(13) : AC1-to-AC0 global command from SPE 4. +event:0x1846 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(14) : AC1-to-AC0 global command from SPE 2. +event:0x1847 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(15) : AC1-to-AC0 global command from SPE 0. +event:0x1848 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(16) : AC1-to-AC0 global command from PPE. +event:0x1849 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(17) : AC1-to-AC0 global command from SPE 1. +event:0x184a counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(18) : AC1-to-AC0 global command from SPE 3. +event:0x184b counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(19) : AC1-to-AC0 global command from SPE 5. +event:0x184c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(20) : AC1-to-AC0 global command from SPE 7. +event:0x184f counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(23) : AC1 sends a global command to AC0. +event:0x1850 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(24) : AC0 reflects a global command back to AC1. +event:0x1851 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1.WAC1_TRCMUX.W_TRCGRP_ACPERF(25) : AC1 reflects a command back to the bus masters. + +# CBE Signal Group 63 - EIB Data Ring Arbitrator - Group 1 (NClk/2) +event:0x189c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPE(0) : Grant on data ring 0. +event:0x189d counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPE(1) : Grant on data ring 1. +event:0x189e counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPE(2) : Grant on data ring 2. +event:0x189f counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPE(3) : Grant on data ring 3. +event:0x18a0 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA.DTRC.TRCGRPE(4) : Data ring 0 is in use. +event:0x18a1 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA.DTRC.TRCGRPE(5) : Data ring 1 is in use. +event:0x18a2 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA.DTRC.TRCGRPE(6) : Data ring 2 is in use. +event:0x18a3 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA.DTRC.TRCGRPE(7) : Data ring 3 is in use. +event:0x18a4 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA.DTRC.TRCGRPE(8) : All data rings are idle. +event:0x18a5 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA.DTRC.TRCGRPE(9) : One data ring is busy. +event:0x18a6 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA.DTRC.TRCGRPE(10) : Two or three data rings are busy. +event:0x18a7 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA.DTRC.TRCGRPE(11) : All data rings are busy. +event:0x18a8 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPE(12) : BIC data request pending. +event:0x18a9 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPE(13) : SPE 6 data request pending. +event:0x18aa counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPE(14) : SPE 4 data request pending. +event:0x18ab counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPE(15) : SPE 2 data request pending. +event:0x18ac counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPE(16) : SPE 0 data request pending. +event:0x18ad counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPE(17) : MIC data request pending. +event:0x18ae counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPE(18) : PPE data request pending. +event:0x18af counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPE(19) : SPE 1 data request pending. +event:0x18b0 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPE(20) : SPE 3 data request pending. +event:0x18b1 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPE(21) : SPE 5 data request pending. +event:0x18b2 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPE(22) : SPE 7 data request pending. +event:0x18b3 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPE(23) : IOC data request pending. +event:0x18b4 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPE(24) : BIC is data destination. +event:0x18b5 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPE(25) : SPE 6 is data destination. +event:0x18b6 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPE(26) : SPE 4 is data destination. +event:0x18b7 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPE(27) : SPE 2 is data destination. +event:0x18b8 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPE(28) : SPE 0 is data destination. +event:0x18b9 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPE(29) : MIC is data destination. +event:0x18ba counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPE(30) : PPE is data destination. +event:0x18bb counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPE(31) : SPE 1 is data destination. + +# CBE Signal Group 64 - EIB Data Ring Arbitrator - Group 2 (NClk/2) +event:0x1900 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPF(0) : BIC data request pending. +event:0x1901 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPF(1) : SPE 6 data request pending. +event:0x1902 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPF(2) : SPE 4 data request pending. +event:0x1903 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPF(3) : SPE 2 data request pending. +event:0x1904 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPF(4) : SPE 0 data request pending. +event:0x1905 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPF(5) : MIC data request pending. +event:0x1906 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPF(6) : PPE data request pending. +event:0x1907 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPF(7) : SPE 1 data request pending. +event:0x1908 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPF(8) : SPE 3 data request pending. +event:0x1909 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPF(9) : SPE 5 data request pending. +event:0x190a counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPF(10) : SPE 7 data request pending. +event:0x190b counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA.DTRC.TRCGRPF(11) : IOC data request pending. +event:0x190c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(12) : BIC is data destination. +event:0x190d counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(13) : SPE 6 is data destination. +event:0x190e counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(14) : SPE 4 is data destination. +event:0x190f counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(15) : SPE 2 is data destination. +event:0x1910 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(16) : SPE 0 is data destination. +event:0x1911 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(17) : MIC is data destination. +event:0x1912 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(18) : PPE is data destination. +event:0x1913 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(19) : SPE 1 is data destination. +event:0x1914 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(20) : SPE 3 is data destination. +event:0x1915 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(21) : SPE 5 is data destination. +event:0x1916 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(22) : SPE 7 is data destination. +event:0x1917 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(23) : IOC is data destination. +event:0x1918 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(24) : Grant on data ring 0. +event:0x1919 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(25) : Grant on data ring 1. +event:0x191a counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(26) : Grant on data ring 2. +event:0x191b counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA.DTRC.TRCGRPF(27) : Grant on data ring 3. +event:0x191c counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA.DTRC.TRCGRPF(28) : All data rings are idle. +event:0x191d counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA.DTRC.TRCGRPF(29) : One data ring is busy. +event:0x191e counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA.DTRC.TRCGRPF(30) : Two or three data rings are busy. +event:0x191f counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA.DTRC.TRCGRPF(31) : All four data rings are busy. + +# CBE Signal Group 651 - EIB Token Manager - Group A0/B0 (NClk/2) +event:0xfe4c counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_e_unused : Even XIO token unused by RAG 0. +event:0xfe4d counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_o_unused : Odd XIO token unused by RAG 0. +event:0xfe4e counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_e_unused : Even bank token unused by RAG 0. +event:0xfe4f counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_o_unused : Odd bank token unused by RAG 0. +event:0xfe54 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc0 : Token granted for SPE 0. +event:0xfe55 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc1 : Token granted for SPE 1. +event:0xfe56 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc2 : Token granted for SPE 2. +event:0xfe57 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc3 : Token granted for SPE 3. +event:0xfe58 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc4 : Token granted for SPE 4. +event:0xfe59 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc5 : Token granted for SPE 5. +event:0xfe5a counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc6 : Token granted for SPE 6. +event:0xfe5b counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc7 : Token granted for SPE 7. + + +# CBE Signal Group 652 - EIB Token Manager - Group A1/B1 (NClk/2) +event:0xfeb0 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_e_wasted : Even XIO token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register. +event:0xfeb1 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_o_wasted : Odd XIO token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register. +event:0xfeb2 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_e_wasted : Even bank token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register. +event:0xfeb3 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_o_wasted : Odd bank token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register. +event:0xfebc counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_xio_e_wasted : Even XIO token wasted by RAG U. +event:0xfebd counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_xio_o_wasted : Odd XIO token wasted by RAG U. +event:0xfebe counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_bank_e_wasted : Even bank token wasted by RAG U. +event:0xfebf counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_bank_o_wasted : Odd bank token wasted by RAG U. + +# CBE Signal Group 653 - EIB Token Manager - Group A2/B2 (NClk/2) +event:0xff14 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_e_shared_to_rag1 : Even XIO token from RAG 0 shared with RAG 1 +event:0xff15 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_e_shared_to_rag2 : Even XIO token from RAG 0 shared with RAG 2 +event:0xff16 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_e_shared_to_rag3 : Even XIO token from RAG 0 shared with RAG 3 +event:0xff17 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_o_shared_to_rag1 : Odd XIO token from RAG 0 shared with RAG 1 +event:0xff18 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_o_shared_to_rag2 : Odd XIO token from RAG 0 shared with RAG 2 +event:0xff19 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_o_shared_to_rag3 : Odd XIO token from RAG 0 shared with RAG 3 +event:0xff1a counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_e_shared_to_rag1 : Even bank token from RAG 0 shared with RAG 1 +event:0xff1b counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_e_shared_to_rag2 : Even bank token from RAG 0 shared with RAG 2 +event:0xff1c counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_e_shared_to_rag3 : Even bank token from RAG 0 shared with RAG 3 +event:0xff1d counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_o_shared_to_rag1 : Odd bank token from RAG 0 shared with RAG 1 +event:0xff1e counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_o_shared_to_rag2 : Odd bank token from RAG 0 shared with RAG 2 +event:0xff1f counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_o_shared_to_rag3 : Odd bank token from RAG 0 shared with RAG 3 + + +# CBE Signal Group 654 - EIB Token Manager - Group A0/B0 (NClk/2) +# Repeat of the 65400, 65401, 65402, 65403, 65416, 65417, 65418, 65419 events + + +# CBE Signal Group 655 - EIB Token Manager - Group A1/B1 (NClk/2) +#repeat of the 65200 events + + +# CBE Signal Group 656 - EIB Token Manager - Group A2/B2 (NClk/2) +event:0x1004f counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_bank_o_shared_to_rag0 : Odd bank token from RAG U shared with RAG 0 +event:0x10050 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_xio_e_shared_to_rag0 : Even XIO token from RAG 1 shared with RAG 0 +event:0x10051 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_xio_e_shared_to_rag2 : Even XIO token from RAG 1 shared with RAG 2 +event:0x10052 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_xio_e_shared_to_rag3 : Even XIO token from RAG 1 shared with RAG 3 +event:0x10053 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_xio_o_shared_to_rag0 : Odd XIO token from RAG 1 shared with RAG 0 +event:0x10054 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_xio_o_shared_to_rag2 : Odd XIO token from RAG 1 shared with RAG 2 +event:0x10055 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_xio_o_shared_to_rag3 : Odd XIO token from RAG 1 shared with RAG 3 +event:0x10056 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_bank_e_shared_to_rag0 : Even bank token from RAG 1 shared with RAG 0 +event:0x10057 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_bank_e_shared_to_rag2 : Even bank token from RAG 1 shared with RAG 2 +event:0x10058 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_bank_e_shared_to_rag3 : Even bank token from RAG 1 shared with RAG 3 +event:0x10059 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_bank_o_shared_to_rag0 : Odd bank token from RAG 1 shared with RAG 0 +event:0x1005a counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_bank_o_shared_to_rag2 : Odd bank token from RAG 1 shared with RAG 2 +event:0x1005b counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_bank_o_shared_to_rag3 : Odd bank token from RAG 1 shared with RAG 3 +event:0x1005c counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_xio_e_shared_to_rag1 : Even XIO token from RAG U shared with RAG 1 +event:0x1005d counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_xio_o_shared_to_rag1 : Odd XIO token from RAG U shared with RAG 1 +event:0x1005e counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_bank_e_shared_to_rag1 : Even bank token from RAG U shared with RAG 1 +event:0x1005f counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_bank_o_shared_to_rag1 : Odd bank token from RAG U shared with RAG 1 + +# CBE Signal Group 657 - EIB Token Manager - Group C0/D0 (NClk/2) +event:0x100e4 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_e_unused : Even XIO token unused by RAG 2 +event:0x100e5 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_o_unused : Odd XIO token unused by RAG 2 +event:0x100e6 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_e_unused : Even bank token unused by RAG 2 +event:0x100e7 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_o_unused : Odd bank token unused by RAG 2 +event:0x100e8 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif0_in_unused : IOIF0 In token unused by RAG 0 +event:0x100e9 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif0_out_unused : IOIF0 Out token unused by RAG 0 +event:0x100ea counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif1_in_unused : IOIF1 In token unused by RAG 0 +event:0x100eb counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif1_out_unused : IOIF1 Out token unused by RAG 0 + + +# CBE Signal Group 658 - EIB Token Manager - Group C1/D1 (NClk/2) +event:0x10148 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_e_wasted : Even XIO token wasted by RAG 2 +event:0x10149 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_o_wasted : Odd XIO token wasted by RAG 2 +event:0x1014a counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_e_wasted : Even bank token wasted by RAG 2 +event:0x1014b counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_o_wasted : Odd bank token wasted by RAG 2 + + +# CBE Signal Group 659 - EIB Token Manager - Group C2/D2 (NClk/2) +event:0x101ac counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_e_shared_to_rag0 : Even XIO token from RAG 2 shared with RAG 0 +event:0x101ad counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_e_shared_to_rag1 : Even XIO token from RAG 2 shared with RAG 1 +event:0x101ae counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_e_shared_to_rag3 : Even XIO token from RAG 2 shared with RAG 3 +event:0x101af counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_o_shared_to_rag0 : Odd XIO token from RAG 2 shared with RAG 0 +event:0x101b0 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_o_shared_to_rag1 : Odd XIO token from RAG 2 shared with RAG 1 +event:0x101b1 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_o_shared_to_rag3 : Odd XIO token from RAG 2 shared with RAG 3 +event:0x101b2 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_e_shared_to_rag0 : Even bank token from RAG 2 shared with RAG 0 +event:0x101b3 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_e_shared_to_rag1 : Even bank token from RAG 2 shared with RAG 1 +event:0x101b4 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_e_shared_to_rag3 : Even bank token from RAG 2 shared with RAG 3 +event:0x101b5 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_o_shared_to_rag0 : Odd bank token from RAG 2 shared with RAG 0 +event:0x101b6 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_o_shared_to_rag1 : Odd bank token from RAG 2 shared with RAG 1 +event:0x101b7 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_o_shared_to_rag3 : Odd bank token from RAG 2 shared with RAG 3 + + +# CBE Signal Group 6510 - EIB Token Manager - Group C3 (NClk/2) +event:0x9ef38 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif0_in_wasted : IOIF0 In token wasted by RAG 0 +event:0x9ef39 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif0_out_wasted : IOIF0 Out token wasted by RAG 0 +event:0x9ef3a counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif1_in_wasted : IOIF1 In token wasted by RAG 0 +event:0x9ef3b counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif1_out_wasted : IOIF1 Out token wasted by RAG 0 + + +# CBE Signal Group 6511 - EIB Token Manager - Group C0/D0 (NClk/2) +# repeat of the events 65764 - 65771 + +# CBE Signal Group 6512 - EIB Token Manager - Group C1/D1 (NClk/2) +event:0x9f010 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_e_wasted : Even XIO token wasted by RAG 3 +event:0x9f011 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_o_wasted : Odd XIO token wasted by RAG 3 +event:0x9f012 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_e_wasted : Even bank token wasted by RAG 3 +event:0x9f013 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_o_wasted : Odd bank token wasted by RAG 3 + +# CBE Signal Group 6513 - EIB Token Manager - Group C2/D2 (NClk/2) +event:0x9f074 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_e_shared_to_rag0 : Even XIO token from RAG 3 shared with RAG 0 +event:0x9f075 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_e_shared_to_rag1 : Even XIO token from RAG 3 shared with RAG 1 +event:0x9f076 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_e_shared_to_rag2 : Even XIO token from RAG 3 shared with RAG 2 +event:0x9f077 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_o_shared_to_rag0 : Odd XIO token from RAG 3 shared with RAG 0 +event:0x9f078 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_o_shared_to_rag1 : Odd XIO token from RAG 3 shared with RAG 1 +event:0x9f079 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_o_shared_to_rag2 : Odd XIO token from RAG 3 shared with RAG 2 +event:0x9f07a counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_e_shared_to_rag0 : Even bank token from RAG 3 shared with RAG 0 +event:0x9f07b counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_e_shared_to_rag1 : Even bank token from RAG 3 shared with RAG 1 +event:0x9f07c counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_e_shared_to_rag2 : Even bank token from RAG 3 shared with RAG 2 +event:0x9f07d counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_o_shared_to_rag0 : Odd bank token from RAG 3 shared with RAG 0 +event:0x9f07e counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_o_shared_to_rag1 : Odd bank token from RAG 3 shared with RAG 1 +event:0x9f07f counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_o_shared_to_rag2 : Odd bank token from RAG 3 shared with RAG 2 + + +# Cell BE Island 7 - Memory Interface Controller (MIC) + +# CBE Signal Group 71 - MIC Group 1 (NClk/2) +event:0x1bc5 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON.YMB_CSR.PERFORM1(1) : XIO1 - Read command queue is empty. +event:0x1bc6 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON.YMB_CSR.PERFORM1(2) : XIO1 - Write command queue is empty. +event:0x1bc8 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON.YMB_CSR.PERFORM1(4) : XIO1 - Read command queue is full. +event:0x1bc9 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON.YMB_CSR.PERFORM1(5) : XIO1 - MIC responds with a Retry for a read command because the read command queue is full. +event:0x1bca counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON.YMB_CSR.PERFORM1(6) : XIO1 - Write command queue is full. +event:0x1bcb counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON.YMB_CSR.PERFORM1(7) : XIO1 - MIC responds with a Retry for a write command because the write command queue is full. +event:0x1bde counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1.YMM_CCS.PERFORM(2) : XIO1 - Read command dispatched; includes high-priority and fast-path reads (see Note 1). +event:0x1bdf counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1.YMM_CCS.PERFORM(3) : XIO1 - Write command dispatched (see Note 1). +event:0x1be0 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1.YMM_CCS.PERFORM(4) : XIO1 - Read-Modify-Write command (data size < 16 bytes) dispatched (see Note 1). +event:0x1be1 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1.YMM_CCS.PERFORM(5) : XIO1 - Refresh dispatched (see Note 1). +event:0x1be3 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1.YMM_CCS.PERFORM(7) : XIO1 - Byte-masking write command (data size >= 16 bytes) dispatched (see Note 1). +event:0x1be5 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1.YMM_CRW.PERFORM(1) : XIO1 - Write command dispatched after a read command was previously dispatched (see Note 1). +event:0x1be6 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1.YMM_CRW.PERFORM(2) : XIO1 - Read command dispatched after a write command was previously dispatched (see Note 1). + + +# CBE Signal Group 72 - MIC Group 2 (NClk/2) +event:0x1c29 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON.YMB_CSR.PERFORM2(1) : XIO0 - Read command queue is empty. +event:0x1c2a counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON.YMB_CSR.PERFORM2(2) : XIO0 - Write command queue is empty. +event:0x1c2c counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON.YMB_CSR.PERFORM2(4) : XIO0 - Read command queue is full. +event:0x1c2d counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON.YMB_CSR.PERFORM2(5) : XIO0 - MIC responds with a Retry for a read command because the read command queue is full. +event:0x1c2e counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON.YMB_CSR.PERFORM2(6) : XIO0 - Write command queue is full. +event:0x1c2f counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON.YMB_CSR.PERFORM2(7) : XIO0 - MIC responds with a Retry for a write command because the write command queue is full. +event:0x1c42 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0.YMM_CCS.PERFORM(2) : XIO0 - Read command dispatched; includes high-priority and fast-path reads (see Note 1). +event:0x1c43 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0.YMM_CCS.PERFORM(3) : XIO0 - Write command dispatched (see Note 1). +event:0x1c44 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0.YMM_CCS.PERFORM(4) : XIO0 - Read-Modify-Write command (data size < 16 bytes) dispatched (see Note 1). +event:0x1c45 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0.YMM_CCS.PERFORM(5) : XIO0 - Refresh dispatched (see Note 1). +event:0x1c49 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0.YMM_CRW.PERFORM(1) : XIO0 - Write command dispatched after a read command was previously dispatched (see Note 1). +event:0x1c4a counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0.YMM_CRW.PERFORM(2) : XIO0 - Read command dispatched after a write command was previously dispatched (see Note 1). + +# CBE Signal Group 73 - MIC Group 3 (NClk/2) +event:0x1ca7 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0.YMM_CCS.PERFORM(3) : XIO0 - Write command dispatched (see Note 1). +event:0x1ca8 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0.YMM_CCS.PERFORM(4) : XIO0 - Read-Modify-Write command (data size < 16 bytes) dispatched (see Note 1). +event:0x1ca9 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0.YMM_CCS.PERFORM(5) : XIO0 - Refresh dispatched (see Note 1). +event:0x1cab counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0.YMM_CCS.PERFORM(7) : XIO0 - Byte-masking write command (data size >= 16 bytes) dispatched (see Note 1). + + +# Cell BE Island 8 - Broadband Engine Interface (BEI) + +# CBE Signal Group 81 - BIF Controller - IOIF0 Word 0 (NClk/2) +event:0x1fb0 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:B2F_Type_A_Data : Type A data physical layer group (PLG). Does not include header-only or credit-only data PLGs. In IOIF mode, counts I/O device read data; in BIF mode, counts all outbound data. +event:0x1fb1 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:B2F_Type_B_Data : Type B data PLG. In IOIF mode, counts I/O device read data; in BIF mode, counts all outbound data. +event:0x1fb2 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:IOC_Type_A_Data : Type A data PLG. Does not include header-only or credit-only PLGs. In IOIF mode, counts CBE store data to I/O device. Does not apply in BIF mode. +event:0x1fb3 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:IOC_Type_B_Data : Type B data PLG. In IOIF mode, counts CBE store data to an I/O device. Does not apply in BIF mode. +event:0x1fb4 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Data_PLG : Data PLG. Does not include header-only or credit-only PLGs. +event:0x1fb5 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Command_PLG : Command PLG (no credit-only PLG). In IOIF mode, counts I/O command or reply PLGs. In BIF mode, counts command/ reflected command or snoop/combined responses. +event:0x1fb6 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_A_Transfer : Type A data transfer regardless of length. Can also be used to count Type A data header PLGs (but not credit-only PLGs). +event:0x1fb7 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_B_Transfer : Type B data transfer. +event:0x1fb8 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Cmd_Credit_Only_PLG : Command-credit-only command PLG in either IOIF or BIF mode. +event:0x1fb9 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Data_Credit_Only_PLG : Data-credit-only data PLG sent in either IOIF or BIF mode. +event:0x1fba counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Non-Null_Envelopes : Non-null envelope sent (does not include long envelopes). +event:0x1fbc counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:null_env_sent : Null envelope sent (see Note 1). +event:0x1fbd counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:no_valid_data : No valid data sent this cycle (see Note 1). +event:0x1fbe counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:norm_env_sent : Normal envelope sent (see Note 1). +event:0x1fbf counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:lnog_env_sent : Long envelope sent (see Note 1). +event:0x1fc0 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:per_mon_null_sent : A Null PLG inserted in an outgoing envelope. +event:0x1fc1 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:per_mon_array_full : Outbound envelope array is full. + +# CBE Signal Group 82 - BIF Controller - IOIF1 Word 0 (NClk/2) +event:0x201b counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_B_Transfer : Type B data transfer. + + +# CBE Signal Group 83 - BIF Controller - IOIF0 Word 2 (NClk/2) +event:0x206d counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:null_env_rcvd : Null envelope received (see Note 1). +event:0x207a counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Command_PLG : Command PLG, but not credit-only PLG. In IOIF mode, counts I/O command or reply PLGs. In BIF mode, counts command/reflected command or snoop/combined responses. +event:0x207b counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Command_Credit_Only_PLG : Command-credit-only command PLG. +event:0x2080 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:norm_env_rcvd_good : Normal envelope received is good (see Note 1). +event:0x2081 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:long_env_rcvd_good : Long envelope received is good (see Note 1). +event:0x2082 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:cmd_credit_only_PLG : Data-credit-only data PLG in either IOIF or BIF mode; will count a maximum of one per envelope (see Note 1). +event:0x2083 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:non-null_envelope : Non-null envelope; does not include long envelopes; includes retried envelopes (see Note 1). +event:0x2084 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:data_grnt_rcvd : Data grant received. +event:0x2088 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Data_PLG : Data PLG. Does not include header-only or credit-only PLGs. +event:0x2089 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_A_transfer : Type A data transfer regardless of length. Can also be used to count Type A data header PLGs, but not credit-only PLGs. +event:0x208a counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_B_transfer : Type B data transfer. + +# CBE Signal Group 84 - BIF Controller - IOIF1 Word 2 (NClk/2) +event:0x20d1 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:null_env_rcvd : Null envelope received (see Note 1). +event:0x20de counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Command_PLG : Command PLG (no credit-only PLG). Counts I/O command or reply PLGs. +event:0x20df counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Command_Credit_Only_PLG : Command-credit-only command PLG. +event:0x20e4 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:norm_env_rcvd_good : Normal envelope received is good (see Note 1). +event:0x20e5 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:long_env_rcvd_good : Long envelope received is good (see Note 1). +event:0x20e6 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:cmd_credit_only_PLG : Data-credit-only data PLG received; will count a maximum of one per envelope (see Note 1). +event:0x20e7 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:non-null_envelope : Non-Null envelope received; does not include long envelopes; includes retried envelopes (see Note 1). +event:0x20e8 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:data_grnt_rcvd : Data grant received. +event:0x20ec counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Data_PLG : Data PLG received. Does not include header-only or credit-only PLGs. +event:0x20ed counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_A_transfer : Type I A data transfer regardless of length. Can also be used to count Type A data header PLGs (but not credit-only PLGs). +event:0x20ee counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_B_transfer : Type B data transfer received. + +# CBE Signal Group 85 - I/O Controller Word 0 - Group 1 (NClk/2) +event:0x213c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:mmio_rd_to_ioif1 : Received MMIO read targeted to IOIF1. +event:0x213d counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:mmio_wrt_to_ioif1 : Received MMIO write targeted to IOIF1. +event:0x213e counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:mmio_rd_to_ioif0 : Received MMIO read targeted to IOIF0. +event:0x213f counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:mmio_wrt_to_ioif0 : Received MMIO write targeted to IOIF0. +event:0x2140 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:cmd_to_slice0 : Sent command to IOIF0. +event:0x2141 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:cmd_to_slice1 : Sent command to IOIF1. + +# CBE Signal Group 86 - I/O Controller Word 2 - Group 2 (NClk/2) +event:0x219d counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:re_dep_dm3 : IOIF0 Dependency Matrix 3 is occupied by a dependent command (see Note 1). +event:0x219e counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:re_dep_dm4 : IOIF0 Dependency Matrix 4 is occupied by a dependent command (see Note 1). +event:0x219f counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:re_dep_dm5 : IOIF0 Dependency Matrix 5 is occupied by a dependent command (see Note 1). +event:0x21a2 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:slice0_ld_rqst : Received read request from IOIF0. +event:0x21a3 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:slice0_str_rqst : Received write request from IOIF0. +event:0x21a6 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:intrpt_from_realizer : Received interrupt from the IOIF0. + +# CBE Signal Group 87 - I/O Controller - Group 3 (NClk/2) +event:0x220c counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn_even : IOIF0 request for token for even memory banks 0-14 (see Note 1). +event:0x220d counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn_odd : IOIF0 request for token for odd memory banks 1-15 (see Note 1). +event:0x220e counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn1/3/5/7 : IOIF0 request for token type 1, 3, 5, or 7 (see Note 1). +event:0x220f counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn9/11/13/15 : IOIF0 request for token type 9, 11, 13, or 15 (see Note 1). +event:0x2214 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn16 : IOIF0 request for token type 16 (see Note 1). +event:0x2215 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn17 : IOIF0 request for token type 17 (see Note 1). +event:0x2216 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn18 : IOIF0 request for token type 18 (see Note 1). +event:0x2217 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn19 : IOIF0 request for token type 19 (see Note 1). + + +# CBE Signal Group 88 - I/O Controller Word 0 - Group 4 (NClk/2) +event:0x2260 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:io_pt_hit : I/O page table cache hit for commands from IOIF. +event:0x2261 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:io_pt_miss : I/O page table cache miss for commands from IOIF. +event:0x2263 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:io_seg_tbl_hit : I/O segment table cache hit. +event:0x2264 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:io_seg_tbl_miss : I/O segment table cache miss. +event:0x2278 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:intrrpt_frm_spu : Interrupt received from any SPU (reflected cmd when IIC has sent ACK response). +event:0x2279 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:iic_intrrpt_to_pu_thrd0 : Internal interrupt controller (IIC) generated interrupt to PPU thread 0. +event:0x227a counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:iic_intrrpt_to_pu_thrd1 : IIC generated interrupt to PPU thread 1. +event:0x227b counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:pu_intrrpt_to_pu_thrd0 : Received external interrupt (using MMIO) from PPU to PPU thread 0. +event:0x227c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:pu_intrrpt_to_pu_thrd1 : Received external interrupt (using MMIO) from PPU to PPU thread 1. +event:0x227c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:pu_intrrpt_to_pu_thrd1 : Received external interrupt (using MMIO) from PPU to PPU thread 1. diff -paurNX diff_file_exclusion oprofile/events/ppc64/cell-be/unit_masks oprofile-with-cell/events/ppc64/cell-be/unit_masks --- oprofile/events/ppc64/cell-be/unit_masks 1969-12-31 18:00:00.000000000 -0600 +++ oprofile-with-cell/events/ppc64/cell-be/unit_masks 2006-11-15 11:32:19.304193144 -0600 @@ -0,0 +1,126 @@ +# Cell Broadband Engine possible unit masks +# +##carll replaced name:zero type:mandatory default:0 +name:zero type:mandatory default:0 + 0x000 Count cycles [mandatory] +name:PPU_0_cycles type:bitmask default:0x013 + 0x001 Count cycles [mandatory] + 0x000 Negative polarity [optional ] + 0x002 Positive polarity [default ] + 0x010 PPU Bus Word 0 [mandatory] +name:PPU_0_edges type:bitmask default:0x012 + 0x000 Count edges [mandatory] + 0x000 Negative polarity [optional ] + 0x002 Positive polarity [default ] + 0x010 PPU Bus Word 0 [mandatory] +name:PPU_2_cycles type:bitmask default:0x043 + 0x001 Count cycles [mandatory] + 0x000 Negative polarity [optional ] + 0x002 Positive polarity [default ] + 0x040 PPU Bus Word 2 [mandatory] +name:PPU_2_edges type:bitmask default:0x042 + 0x000 Count edges [mandatory] + 0x000 Negative polarity [optional ] + 0x002 Positive polarity [default ] + 0x040 PPU Bus Word 2 [mandatory] +name:PPU_01_cycles type:bitmask default:0x023 + 0x001 Count cycles [mandatory] + 0x000 Negative polarity [optional ] + 0x002 Positive polarity [default ] + 0x010 PPU Bus Word 0 [optional ] + 0x020 PPU Bus Word 1 [default ] +name:PPU_01_edges type:bitmask default:0x022 + 0x000 Count edges [mandatory] + 0x000 Negative polarity [optional ] + 0x002 Positive polarity [default ] + 0x010 PPU Bus Word 0 [optional ] + 0x020 PPU Bus Word 1 [default ] +name:PPU_01_cycles_or_edges type:bitmask default:0x023 + 0x000 Count edges [optional ] + 0x001 Count cycles [default ] + 0x000 Negative polarity [optional ] + 0x002 Positive polarity [default ] + 0x010 PPU Bus Word 0 [optional ] + 0x020 PPU Bus Word 1 [default ] +name:PPU_02_cycles type:bitmask default:0x013 + 0x001 Count cycles [mandatory] + 0x000 Negative polarity [optional ] + 0x002 Positive polarity [default ] + 0x010 PPU Bus Word 0 [default ] + 0x040 PPU Bus Word 2 [optional ] +name:PPU_02_edges type:bitmask default:0x012 + 0x000 Count edges [mandatory] + 0x000 Negative polarity [optional ] + 0x002 Positive polarity [default ] + 0x010 PPU Bus Word 0 [default ] + 0x040 PPU Bus Word 2 [optional ] +name:PPU_02_cycles_or_edges type:bitmask default:0x013 + 0x000 Count edges [optional ] + 0x001 Count cycles [default ] + 0x000 Negative polarity [optional ] + 0x002 Positive polarity [default ] + 0x010 PPU Bus Word 0 [default ] + 0x040 PPU Bus Word 2 [optional ] +name:PPU_0123_cycles type:bitmask default:0x033 + 0x001 Count cycles [mandatory] + 0x000 Negative polarity [optional ] + 0x002 Positive polarity [default ] + 0x030 PPU Bus Word 0/1 [default ] + 0x0c0 PPU Bus Word 2/3 [optional ] +name:SPU_0_edges type:bitmask default:0x0112 + 0x0000 Count edges [mandatory] + 0x0000 Negative polarity [optional ] + 0x0002 Positive polarity [default ] + 0x0110 SPU Bus Word 0 [mandatory] + 0x0000 SPU 0 [default ] + 0x1000 SPU 1 [optional ] + 0x2000 SPU 2 [optional ] + 0x3000 SPU 3 [optional ] + 0x4000 SPU 4 [optional ] + 0x5000 SPU 5 [optional ] + 0x6000 SPU 6 [optional ] + 0x7000 SPU 7 [optional ] +name:SPU_02_cycles type:bitmask default:0x0113 + 0x0001 Count cycles [mandatory] + 0x0000 Negative polarity [optional ] + 0x0002 Positive polarity [default ] + 0x0110 SPU Bus Word 0 [default ] + 0x0140 SPU Bus Word 2 [optional ] + 0x0000 SPU 0 [default ] + 0x1000 SPU 1 [optional ] + 0x2000 SPU 2 [optional ] + 0x3000 SPU 3 [optional ] + 0x4000 SPU 4 [optional ] + 0x5000 SPU 5 [optional ] + 0x6000 SPU 6 [optional ] + 0x7000 SPU 7 [optional ] +name:SPU_02_edges type:bitmask default:0x0112 + 0x0000 Count edges [mandatory] + 0x0000 Negative polarity [optional ] + 0x0002 Positive polarity [default ] + 0x0110 SPU Bus Word 0 [default ] + 0x0140 SPU Bus Word 2 [optional ] + 0x0000 SPU 0 [default ] + 0x1000 SPU 1 [optional ] + 0x2000 SPU 2 [optional ] + 0x3000 SPU 3 [optional ] + 0x4000 SPU 4 [optional ] + 0x5000 SPU 5 [optional ] + 0x6000 SPU 6 [optional ] + 0x7000 SPU 7 [optional ] +name:SPU_Event_edges type:bitmask default:0x0146 + 0x0000 Count edges [mandatory] + 0x0000 Negative polarity [optional ] + 0x0002 Positive polarity [default ] + 0x0144 SPU Event 0 [default ] + 0x0154 SPU Event 1 [optional ] + 0x0164 SPU Event 2 [optional ] + 0x0174 SPU Event 3 [optional ] + 0x0000 SPU 0 [default ] + 0x1000 SPU 1 [optional ] + 0x2000 SPU 2 [optional ] + 0x3000 SPU 3 [optional ] + 0x4000 SPU 4 [optional ] + 0x5000 SPU 5 [optional ] + 0x6000 SPU 6 [optional ] + 0x7000 SPU 7 [optional ] diff -paurNX diff_file_exclusion oprofile/libop/op_cpu_type.c oprofile-with-cell/libop/op_cpu_type.c --- oprofile/libop/op_cpu_type.c 2006-08-22 16:24:32.000000000 -0500 +++ oprofile-with-cell/libop/op_cpu_type.c 2006-11-15 11:32:19.306192840 -0600 @@ -47,6 +47,7 @@ static struct cpu_descr const cpu_descrs { "ppc64 POWER5", "ppc64/power5", CPU_PPC64_POWER5, 6 }, { "ppc64 POWER5+", "ppc64/power5+", CPU_PPC64_POWER5p, 6 }, { "ppc64 970", "ppc64/970", CPU_PPC64_970, 8 }, + { "ppc64 Cell Broadband Engine", "ppc64/cell-be", CPU_PPC64_CELL, 8 }, { "MIPS 20K", "mips/20K", CPU_MIPS_20K, 1}, { "MIPS 24K", "mips/24K", CPU_MIPS_24K, 2}, { "MIPS 25K", "mips/25K", CPU_MIPS_25K, 2}, diff -paurNX diff_file_exclusion oprofile/libop/op_cpu_type.h oprofile-with-cell/libop/op_cpu_type.h --- oprofile/libop/op_cpu_type.h 2006-08-22 16:24:32.000000000 -0500 +++ oprofile-with-cell/libop/op_cpu_type.h 2006-11-15 11:32:19.307192688 -0600 @@ -43,6 +43,7 @@ typedef enum { CPU_PPC64_POWER5, /**< ppc64 POWER5 family */ CPU_PPC64_POWER5p, /**< ppc64 Power5+ family */ CPU_PPC64_970, /**< ppc64 970 family */ + CPU_PPC64_CELL, /**< ppc64 Cell Broadband Engine*/ CPU_MIPS_20K, /**< MIPS 20K */ CPU_MIPS_24K, /**< MIPS 24K */ CPU_MIPS_25K, /**< MIPS 25K */ diff -paurNX diff_file_exclusion oprofile/libop/op_events.c oprofile-with-cell/libop/op_events.c --- oprofile/libop/op_events.c 2006-11-15 09:46:28.000000000 -0600 +++ oprofile-with-cell/libop/op_events.c 2006-11-15 11:32:19.310192232 -0600 @@ -789,6 +789,7 @@ void op_default_event(op_cpu cpu_type, s case CPU_PPC64_POWER4: case CPU_PPC64_POWER5: case CPU_PPC64_POWER5p: + case CPU_PPC64_CELL: descr->name = "CYCLES"; break; diff -paurNX diff_file_exclusion oprofile/utils/ophelp.c oprofile-with-cell/utils/ophelp.c --- oprofile/utils/ophelp.c 2006-09-20 20:26:15.000000000 -0500 +++ oprofile-with-cell/utils/ophelp.c 2006-11-15 11:32:19.313191776 -0600 @@ -419,6 +419,11 @@ int main(int argc, char const * argv[]) "http://www-306.ibm.com/chips/techlib/techlib.nsf/productfamilies/PowerPC\n"); break; + case CPU_PPC64_CELL: + printf("Obtain Cell Broadband Engine documentation at:\n" + "http://www-306.ibm.com/chips/techlib/techlib.nsf/products/Cell_Broadband_Engine\n"); + break; + case CPU_MIPS_20K: printf("See Programming the MIPS64 20Kc Processor Core User's " "manual available from www.mips.com\n");